Method of fabricating power semiconductor device
First Claim
1. A method of fabricating power semiconductor device, comprising:
- providing a substrate having an original top surface and a bottom surface;
etching the substrate through a first mask to form a first trench and at least a second trench, wherein a width of the first trench is greater than a width of the at least a second trench;
forming a gate insulating layer all over the substrate to cover the original top surface and sidewalls and bottoms of the first trench and the at least a second trench;
performing a first deposition process to form a first gate material layer all over the gate insulating layer, wherein the first trench is not fully filled with the first gate material layer;
performing an isotropic or anisotropic etching back process to remove the first gate material layer within the first trench and above the original top surface of the substrate;
performing a tilt ion implantation process all over the substrate to form a first dopant layer in a surface layer of the substrate, the surface layer of the substrate comprising a surface layer of the original top surface of the substrate and a surface layer of the sidewall and the bottom of the first trench;
performing a second deposition process all over the substrate to form a second gate material layer, wherein, the first gate material layer combines the second gate material layer to form a gate material layer, and the gate material layer fills up the first trench and the at least a second trench and covers the gate insulation layer on the original top surface of the substrate;
performing an anisotropic etching back process to partially remove the gate material layer, thereby exposing the gate insulation layer on the original top surface of the substrate;
performing a first ion implantation all over the substrate to form a second dopant layer in a surface of the original top surface of the substrate; and
performing a drive-in process to extend the distribution of the dopants of the first dopant layer and the second dopant layer in the substrate, thereby to form a base in the substrate and to form a bottom-lightly-doped layer surrounding a bottom of the first trench and adjacent to the base.
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Accused Products
Abstract
Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.
40 Citations
13 Claims
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1. A method of fabricating power semiconductor device, comprising:
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providing a substrate having an original top surface and a bottom surface; etching the substrate through a first mask to form a first trench and at least a second trench, wherein a width of the first trench is greater than a width of the at least a second trench; forming a gate insulating layer all over the substrate to cover the original top surface and sidewalls and bottoms of the first trench and the at least a second trench; performing a first deposition process to form a first gate material layer all over the gate insulating layer, wherein the first trench is not fully filled with the first gate material layer; performing an isotropic or anisotropic etching back process to remove the first gate material layer within the first trench and above the original top surface of the substrate; performing a tilt ion implantation process all over the substrate to form a first dopant layer in a surface layer of the substrate, the surface layer of the substrate comprising a surface layer of the original top surface of the substrate and a surface layer of the sidewall and the bottom of the first trench; performing a second deposition process all over the substrate to form a second gate material layer, wherein, the first gate material layer combines the second gate material layer to form a gate material layer, and the gate material layer fills up the first trench and the at least a second trench and covers the gate insulation layer on the original top surface of the substrate; performing an anisotropic etching back process to partially remove the gate material layer, thereby exposing the gate insulation layer on the original top surface of the substrate; performing a first ion implantation all over the substrate to form a second dopant layer in a surface of the original top surface of the substrate; and performing a drive-in process to extend the distribution of the dopants of the first dopant layer and the second dopant layer in the substrate, thereby to form a base in the substrate and to form a bottom-lightly-doped layer surrounding a bottom of the first trench and adjacent to the base. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification