APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM

• US 20100287323A1
• Filed: 07/20/2010
• Published: 11/11/2010
• Est. Priority Date: 02/05/2004
• Status: Active Grant

• Current Assignee: Douglas A. Larson, Jeffrey J. Cronin
• Original Assignee: Douglas A. Larson, Jeffrey J. Cronin
• Inventors: Larson, Douglas A., Cronin, Jeffrey J.
• Granted Patent: US 8,291,173 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Claims

1. (canceled)

2. A logic circuit, comprising:

first and second data bus interfaces configured to be coupled to a bidirectional data bus;

a data path configured to transfer read and write data between the first and second bus interfaces; and

a bypass circuit coupled to the first and second data bus interfaces and configured to store write data from the bidirectional data bus to transfer the write data from one data bus interface to the other instead of over the data path and configured to restore stored write data to the bidirectional data bus to complete the transfer of the write data.

3. The logic circuit of claim 2 wherein the bypass circuit comprises:

a first buffer having an input and an output, the input configured to be coupled to the bidirectional bus;

a register having an input configured to be coupled to the output of the first buffer and further having an output;

a multiplexer having a first input configured to be coupled to the output of the first buffer and a second input configured to be coupled to the output of the register, the multiplexer further having a selection terminal and an output;

a second buffer having an input configured to be coupled to the output of the multiplexer, an output configured to be coupled to the bidirectional data bus, and an activation terminal; and

bypass control logic configured to generate a control signal applied to the selection terminal to control the multiplexer and applied to the activation terminal to control the second buffer.

4. The logic circuit of claim 2 wherein the logic circuit is embedded in a die.

5. The logic circuit of claim 2, further comprising a memory device interface configured to couple to at least one memory device.

6. The logic circuit of claim 2, further comprising control logic coupled to the bypass circuit and configured to generate a control signal to control the bypass circuit to store the write data and restore the write data.

7. The logic circuit of claim 2 wherein the bypass circuit is configured to store the write data and restore the write data responsive at least in part to a control signal provided by a memory controller.

8. The logic circuit of claim 2 wherein the logic circuit is included in a memory hub.

9. The logic circuit of claim 2 wherein the bypass circuit is configured to decouple and temporarily store write data from the bidirectional data bus in a data storage device during the execution of a read operation and restore the decoupled write data to the bidirectional data bus once the read operation has ended.

10. A memory logic circuit comprising:

first and second data bus interfaces coupled to a bidirectional data bus;

a data link configured to transfer read or write data between the first and second data bus interfaces;

a bypass circuit coupled to the data link and configured to store write data therefrom while read data is transferred over the data link and restore write data to the data link when the read data has finished transmitting; and

control logic configured to control the bypass circuit responsive at least in part to a bypass signal.

11. The memory logic circuit of claim 10, further comprising a first memory interface configured to couple memory commands to at least one memory.

12. The memory logic circuit of claim 10 wherein the first or second data bus interface is configured to be coupled to a memory controller via the bidirectional bus.

13. The memory logic circuit of claim 10 wherein the bypass circuit is configured to store write data in a FIFO register.

14. The memory logic circuit of claim 10 wherein the bypass circuit comprises a non-bypass write data path and a bypass write data path having a bypass register configured to store the write data.

15. The memory logic circuit of claim 10 wherein the write data is transferred back to the bidirectional data bus a specified amount of time after it is stored.

16. The memory logic circuit of claim 10 wherein the memory logic circuit is included in a memory hub.

17. A method of managing read and write data transmission in a memory logic circuit, comprising:

enabling a write data bypass circuit to decouple and store write data from a bidirectional bus responsive at least in part to receipt of a read operation and transmission of the same further downstream on the bidirectional bus and issuance of a write command; and

restoring the write data to the bidirectional data bus responsive at least in part to read data passing upstream on the bidirectional data bus.

18. A write data bypass circuit to store and transmit write data on a bidirectional memory bus, comprising:

a first buffer coupled to the bidirectional bus configured to receive data from and transmit data to the bidirectional data bus;

a data storage device configured to receive and store write data from the bidirectional data bus during the execution of a read operation to prevent a data collision;

a multiplexer configured to select between the output of the first buffer or the data storage device;

a second buffer coupled to the multiplexer and configured to be enabled or disabled to control output from the write data bypass circuit; and

bypass control logic configured to control the multiplexer and the second buffer in order to restore write data to the bidirectional data bus.

19. The write data bypass circuit of claim 18 wherein the data storage device comprises a FIFO register.