Wake-and-Go Mechanism with System Address Bus Transaction Master

• US 20100287341A1
• Filed: 02/01/2008
• Published: 11/11/2010
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Granted Patent: US 8,127,080 B2
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address and snoops the target address on the system bus.

Claims

1. A method, in a data processing system, for performing a look-ahead operation in a wake-and-go mechanism, the method comprising:

issuing a look-ahead load command on a system bus to read a data value from a target address;

performing a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred;

in response to the comparison resulting in a determination that the event has not occurred, populating a wake-and-go storage array with the target address; and

snooping the target address on the system bus.

2. The method of claim 1, wherein the look-ahead load command is a load without reservation command.

3. The method of claim 1, wherein the look-ahead load command is a specialized bus command indicating that the wake-and-go mechanism is performing a look-ahead polling operation without caching or data exclusivity.

4. The method of claim 1, further comprising:

in response to the comparison resulting in a determination that the event has occurred, issuing a load with reservation command on the system bus.

5. The method of claim 1, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

6. The method of claim 5, wherein responsive to detecting the event, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

7. The method of claim 1, wherein the event is a direct memory access operation that moves data from a source address to the target address.

8. A data processing system, comprising:

a wake-and-go mechanism; and

a wake-and-go storage array,

wherein the wake-and-go mechanism is configured to;

issue a look-ahead load command on a system bus to read a data value from a target address;

perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred;

in response to the comparison resulting in a determination that the event has not occurred, populate the wake-and-go storage array with the target address; and

snoop the target address on the system bus.

9. The data processing system of claim 8, wherein the look-ahead load command is a load without reservation command.

10. The data processing system of claim 8, wherein the look-ahead load command is a specialized bus command indicating that the wake-and-go mechanism is performing a look-ahead polling operation without caching or data exclusivity.

11. The data processing system of claim 8, wherein the wake-and-go mechanism is further configured to:

in response to the comparison resulting in a determination that the event has occurred, issue a load with reservation command on the system bus.

12. The data processing system of claim 8, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

13. The data processing system of claim 12, wherein responsive to detecting the event, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

14. The data processing system of claim 8, wherein the event is a direct memory access operation that moves data from a source address to the target address.

15. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

issue a look-ahead load command on a system bus to read a data value from a target address;

perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred;

in response to the comparison resulting in a determination that the event has not occurred, populate a wake-and-go storage array with the target address; and

snoop the target address on the system bus.

16. The computer program product of claim 15, wherein the look-ahead load command is a load without reservation command.

17. The computer program product of claim 15, wherein the look-ahead load command is a specialized bus command indicating that the wake-and-go mechanism is performing a look-ahead polling operation without caching or data exclusivity.

18. The computer program product of claim 15, wherein the computer readable program further causes the computing device to:

in response to the comparison resulting in a determination that the event has occurred, issue a load with reservation command on the system bus.

19. The computer program product of claim 15, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

20. The computer program product of claim 15, wherein the event is a direct memory access operation that moves data from a source address to the target address.