Protecting Hardware Circuit Design by Secret Sharing

• US 20100287374A1
• Filed: 03/09/2010
• Published: 11/11/2010
• Est. Priority Date: 03/09/2009
• Status: Active Grant

• Current Assignee: Rice University, Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Rice University, Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Koushanfar, Farinaz, Roy, Jarrod A., Markov, Igor L.
• Granted Patent: US 8,732,468 B2
• Time in Patent Office: Days
• US Class Current: 713/171
• CPC Class Codes: G06F 21/70 Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices

Abstract

Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.

Claims

1. A method for locking a bus in a digital bus-based device, the method comprising:

the digital bus-based device generating a first unique identification data (ID) for the device such that the first unique ID is different than IDs for a plurality of other digital bus-based devices fabricated along with the digital bus-based device;

an authenticator external to the digital bus-based device generating a second unique ID for the digital bus-based device, where both the authenticator and the digital bus-based device apply a first transformation rule on their respective first and second unique IDs;

communicating the first unique ID, applied to the transformation rule, from the digital bus-based device to the authenticator and in response the authenticator determining a first secret authentication key derived from the received first unique ID applied to the transformation rule;

communicating the second unique ID, applied to the transformation rule, from the authenticator to the digital bus-based device and in response encrypting the semiconductor bus-based device with a second secret authentication key derived from the received second unique ID applied to the transformation rule; and

communicating the first secret authentication key to the digital bus-based device, wherein the digital bus-based device determines if the first secret authentication key is the same as the second secret authentication key in which case the bus in the digital bus-based device is activated, wherein if the first secret authentication key is not the same as the second secret authentication key, the bus in the digital bus-based device is not activated.

2. The method of claim 1, wherein the bus is a system bus for the device, a bus for a particular sub-system of the device, an external interface bus, or an input/output bus.

3. The method of claim 1, wherein the first unique ID is a first Diffie-Hellman (D-H) determined secret value and the wherein the second unique ID is a second D-H determined secret value, and wherein the authenticator and the digital bus-based device communicate according to a D-H protocol.

4. The method of claim 1, wherein the digital bus-based device is an application specific integrated circuit, field programmable gate array, System-on-a-chip, microprocessor, digital signal processor, graphics processing unit, central processing unit, network processor, embedded processor, or a memory controller.

5. The method of claim 1, wherein the first unique ID and the second unique ID are generated randomly.

6. The method of claim 5, wherein the random first unique ID and the random second unique ID are generated using at least one of timing fluctuations, power fluctuations, or other fluctuations in physical parameters of the digital bus-based device.

7. The method of claim 6, wherein the random first unique ID and the random second unique ID are generated using at least two of the timing fluctuations, the power fluctuations, or the other fluctuations in physical parameters of the digital bus-based device.

8. The method of claim 1, wherein at least one of the first authentication key and the second authentication key has a length of at least 64 bits.

9. The method of claim 1, wherein the authenticator determines the first secret authentication key using a one-way function, and wherein the digital bus-based device determines a second secret authentication key using the one-way function.

10. The method of claim 1, wherein the first secret authentication key is communicated to the semiconductor bus-based device on a dedicated authentication connector pin of the device.

11. The method of claim 1, wherein the transformation rule is a modulo function.

12. The method of claim 1, wherein the digital bus-based device is a semiconductor device.

13. A method for controlling activation of an integrated circuit (IC) having a unique IC identification data, the method comprising:

an authenticator external to the integrated circuit generating a unique authenticator identification data corresponding to the IC, the authenticator being coupled to the IC through a bus;

applying a transformation rule to the unique IC identification data and to the unique authenticator identification data to form a transformed IC identification data and a transformed authenticator identification data, respectively;

sharing the transformed IC identification data and the transformed authenticator identification data;

deriving a first secret authentication key from the transformed IC identification data and deriving a second secret authentication key from the authenticator identification data; and

encrypting the IC using the second secret authentication key, wherein the IC is deactivated unless the IC receives the first secret authentication key and determines that a comparison of the received first secret authentication key and the second secret authentication key is valid.

14. The method of claim 13, further comprising:

communicating the first secret authentication key to the IC over the bus;

the IC comparing the first secret authentication key to the second secret authentication key; and

in response to the comparison of the first secret authentication key and the second secret authentication key, activating the IC device for operation if the comparison is valid or deactivating the IC device to block operation if the comparison is invalid.

15. The method of claim 13, wherein the bus is a system bus for the IC, a bus for a particular sub-system of the IC, an external interface bus, or an input/output bus.

16. The method of claim 13, wherein the unique IC identification data is a first Diffie-Hellman (D-H) determined secret value and the wherein the unique authenticator identification data is a second D-H determined secret value, and wherein the authenticator and the IC communicate according to a D-H protocol.

17. The method of claim 13, further comprising:

the IC randomly determining the unique IC identification data; and

the authenticator randomly determining the authenticator identification data.

18. The method of claim 17, wherein the unique IC identification data and the unique authenticator identification data are randomly determined using at least one of timing fluctuations, power fluctuations, or other fluctuations in physical parameters of the IC.

19. The method of claim 17, wherein the unique IC identification data and the unique authenticator identification data are randomly determined using two or more of the timing fluctuations, the power fluctuations, or the other fluctuations in the physical parameters of the IC.

20. The method of claim 13, wherein the IC is an application specific integrated circuit, field programmable gate array, System-on-a-chip, microprocessor, digital signal processor, graphics processing unit, central processing unit, network processor, embedded processor, or a memory controller.

21. The method of claim 13, wherein at least one of the first authentication key and the second authentication key has a length of at least 64 bits.

22. The method of claim 13, further comprising:

the authenticator deriving the first secret authentication key from the transformed IC identification data using a one-way function; and

the IC deriving the second secret authentication key from the authenticator identification data using the one-way function.

23. The method of claim 13, further comprising communicating the first secret authentication key to the IC on a dedicated authentication connector pin of the IC.

24. The method of claim 13, wherein the transformation rule is a modulo function.