Flash Memory Device and Flash Memory Programming Method Equalizing Wear-Level

• US 20100287427A1
• Filed: 08/25/2008
• Published: 11/11/2010
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: OCZ Storage Solutions Incorporated (Toshiba Corporation)
• Inventors: Kim, Bumsoo, Park, Hanmook, Chung, Hyunmo
• Granted Patent: US 8,756,464 B2
• Time in Patent Office: Days
• US Class Current: 714/721
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 16/1847 specifically adapted to static storage, e.g. adapted to flash memory or SSD
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters

Abstract

Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell.

Claims

1. A memory device, comprising:

a memory cell array;

an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘

1’

s and ‘

0’

s in the data page;

a programming unit to store the generated programming page in the memory cell array; and

a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page.

2. The memory device of claim 1, wherein the inversion determining unit generates the programming page through inverting the data page when the number of ‘

0’

s is greater than the number of ‘

1’

s in the data page.

3. The memory device of claim 1, wherein the inversion determining unit determines whether to perform inversion of the data page to make a number of memory cells with a threshold voltage that varies less than a number of memory cells with a threshold voltage that does not vary in the memory cell array, while the programming unit stores the programming page.

4. The memory device of claim 1, wherein the data verifying unit inverts the read programming page to restore the data page when the error exists in the read programming page.

5. The memory device of claim 1, wherein the data verifying unit verifies existence of the error through either Error Correction Codes (ECC) decoding the read programming page or checking a parity of the read programming page.

6. The memory device of claim 1, wherein information about whether the programming page is generated through inversion of the data page is not stored in the memory cell array.

7. A memory device, comprising:

a memory cell array;

a page dividing unit to divide a data page into a plurality of data sub-pages;

an inversion determining unit to generate each programming page corresponding to each of the data sub-pages through inverting or not inverting each of the data sub-pages based on a number of ‘

1’

s and ‘

0’

s in each of the data sub-pages; and

a programming unit to store each generated programming page to the memory cell array.

8. The memory device of claim 7, wherein the programming unit stores an inversion flag denoting whether each of the data sub-pages is inverted in the memory cell array

9. The memory device of claim 8, further comprising:

a data verifying unit to read each programming page stored in the memory cell array and the inversion flag stored in the memory cell array, to restore the data page through inverting or not inverting the read programming page depending on the read inversion flag, and to output the restored data page.

10. The memory device of claim 7, further comprising:

a data verifying unit to read each programming page stored in the memory cell array, to restore each of the data sub-pages from the programming page depending on whether an error exists in each read programming page, to combine each of the restored data sub-pages to restore the data page, and to output the restored data page.

11. The memory device of claim 10, wherein the data verifying unit restores each of the data sub-pages through inverting each read programming page, when the error exists in the read programming page.

12. The memory device of claim 10, wherein the data verifying unit verifies existence of the error through either ECC decoding each read programming page or checking a parity of the read programming page.

13. The memory device of claim 7, wherein the inversion determining unit generates the programming page through inverting each of the data sub-pages when the number of ‘

0’

s is greater than the number of ‘

1’

s in each of the data sub-pages.

14. The memory device of claim 7, wherein the inversion determining unit determines whether to perform inversion of each of the data sub-pages to make a number of memory cells having a threshold voltage that varies less than a number of memory cells having a threshold voltage that does not vary in the memory cell array, while the programming unit stores each programming page.

15. A memory programming method, the method comprising:

determining whether to perform inversion of a data page based on a number of ‘

1’

s and ‘

0’

s in the data page;

generating a programming page from the data page according to the determination on whether to perform inversion of the data page;

storing the generated programming page in a memory cell array;

reading the programming page stored in the memory cell array;

determining whether to perform inversion of the read programming page depending on whether an error exists in the read programming page; and

restoring the data page from the read programming page according to the determination on whether to perform inversion of the read programming page.

16. The method of claim 15, wherein the generating of the programming page from the data page determines to perform inversion of the data page when a number of ‘

0’

s is greater than a number of ‘

1’

s in the data page.

17. The method of claim 15, wherein the determining of whether to perform inversion of the read programming page determines to perform inversion of the read programming page when the error exists in the read programming page.

18. A memory programming method, the method comprising:

dividing a data page into a plurality of data sub-pages;

determining whether to perform inversion of each of the data sub-page based on a number of ‘

1’

s and ‘

0’

s in the each of the data sub-pages;

generating a programming page corresponding to each of the data sub-pages from each of the data sub-pages according to the determination on whether to perform inversion of each of the data sub-pages; and

storing each generated programming page to the memory cell array.

19. The method of claim 18, further comprising:

storing an inversion flag denoting whether each of the data sub-pages is inverted in the memory cell array;

reading each programming page stored in the memory cell array and the inversion flag stored in the memory cell array;

restoring each of the data sub-pages through inverting or not inverting each read programming page depending on the read inversion flag; and

restoring the data page through combining each restored data sub-pages.

20. The method of claim 18, further comprising:

reading each programming page stored in the memory cell array;

determining whether to perform inversion of each read programming page depending on whether an error exists in each read programming page;

restoring each of the data sub-pages from each read programming page according to the determination on whether to perform inversion of each of the read programming page; and

restoring the data page through combining each restored data sub-page.

21. A computer readable recording device storing a program for implementing a memory programming method, the method comprising:

determining whether to perform inversion of a data page based on a number of ‘

1’

s and ‘

0’

s in the data page;

generating a programming page from the data page according to the determination on whether to perform inversion of the data page;

storing the generated programming page in a memory cell array;

reading the programming page stored in the memory cell array;

determining whether to perform inversion of the read programming page depending on whether an error exists in the read programming page; and

restoring the data page from the read programming page according to the determination on whether to perform inversion of the read programming page.

22. A computer readable recording device storing a program for implementing a memory programming method, the method comprising:

dividing a data page into a plurality of data sub-pages;

determining whether to perform inversion of each of the data sub-page based on a number of ‘

1’

s and ‘

0’

s in the each of the data sub-pages;

generating a programming page corresponding to each of the data sub-pages from each of the data sub-pages according to the determination on whether to perform inversion of each of the data sub-pages; and

storing each generated programming page to the memory cell array.