THIN FILM TRANSISTOR ARRAY SUBSTRATE, DISPLAY PANEL COMPRISING THE SAME, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE

• US 20100289025A1
• Filed: 08/05/2008
• Published: 11/18/2010
• Est. Priority Date: 12/11/2007
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakagawa, Hidetoshi
• Granted Patent: US 8,314,424 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A TFT (5) includes: a gate electrode (12a); a first semiconductor portion (14a) that overlaps the gate electrode (12a) having the gate insulating film (13) interposed therebetween; a source electrode (15a) and a drain electrode (15b) that overlap the gate electrode (12a) having the gate insulating film (13) and the first semiconductor portion (14a) interposed therebetween; a second semiconductor portion (14b) that overlaps the gate electrode (12a) between the gate insulating film (13) and the source electrode (15a); and a conductive portion (15c) that overlaps the gate electrode (12a) having the gate insulating film (13) and the second semiconductor portion (14b) interposed therebetween. The TFT (5) brings the source line (15a) and the pixel electrode (17) into conduction by a switching element that includes short-circuit portion at the source electrode (15a) and the drain electrode (15b), the second semiconductor portion (14b) and the conductive portion (15c).

Claims

1. A thin film transistor array substrate, comprising:

a plurality of pixel electrodes arranged in a matrix pattern;

a plurality of source lines arranged to extend in parallel to one another and each arranged between the pixel electrodes;

a plurality of gate lines arranged to extend in parallel to one another and in a direction crossing the source lines; and

a plurality of thin film transistors respectively provided per each of intersections of the gate lines and the source lines, wherein

the thin film transistors each include;

a gate electrode connected to corresponding one of the gate lines;

a first semiconductor portion formed to be island-shaped and to overlap the gate electrode having a gate insulating film interposed therebetween;

a source electrode arranged to overlap the gate electrode having the gate insulating film and the first semiconductor portion interposed therebetween and connected to corresponding one of the source lines, a drain electrode arranged to overlap the gate electrode having the gate insulating film and the first semiconductor portion interposed therebetween and connected to corresponding one of the pixel electrodes;

a second semiconductor portion formed to be island-shaped between the gate insulating film and the source electrode so as to overlap the gate electrode, and a conductive portion arranged to overlap the gate electrode having the gate insulating film and the second semiconductor portion interposed therebetween, and wherein

the thin film transistors are each configured such that, when a short-circuit portion is formed by a short-circuit established at the source electrode and the drain electrode, the source line connected to the source electrode and the pixel electrode connected to the drain electrode are brought into conduction by a switching element including the short-circuit portion, the second semiconductor portion and the conductive portion.

2. The thin film transistor array substrate of claim 1, wherein

the conductive portion is a bypass wiring arranged for each of the source lines per each of the intersections of the gate lines and the source lines, and extends along each of the source lines.

3. The thin film transistor array substrate of claim 2, wherein

a channel width and a channel length of the first semiconductor portion defined by the source electrode and the drain electrode are set to be equal to a channel width and a channel length of the second semiconductor portion defined by the source electrode and the bypass wiring.

4. The thin film transistor array substrate of claim 2, wherein

the gate electrode is structured with part of the corresponding one of the gate lines, and the corresponding one of the gate lines is provided with a slit formed around the source electrode and the drain electrode.

5. The thin film transistor array substrate of claim 2, wherein

the gate electrode has a protrusion portion in which the corresponding one of the gate lines is protruding sideways, and

the source electrode and the drain electrode are arranged so as to overlap the protrusion portion.

6. The thin film transistor array substrate of claim 1, wherein

the conductive portion is a floating electrode arranged per each of the intersections of the gate lines and the source lines, and extends along the source electrode, and

the gate electrode is structured with part of the corresponding one of the gate lines, and the corresponding one of the gate lines is provided with a slit formed so as to cross the drain electrode and the floating electrode.

7. A display panel, comprising:

the thin film transistor array substrate of claim 1;

a counter substrate disposed to oppose to the thin film transistor array substrate; and

a display medium layer arranged between the thin film transistor array substrate and the counter substrate.

8. A method for manufacturing a thin film transistor array substrate, the thin film transistor array substrate including:

a plurality of pixel electrodes arranged in a matrix pattern;

a plurality of source lines arranged to extend in parallel to one another and each arranged between the pixel electrodes;

a plurality of gate lines arranged to extend in parallel to one another and in a direction crossing the source lines; and

a plurality of thin film transistors respectively provided per each of intersections of the gate lines and the source lines, wherein

the thin film transistors each include;

a gate electrode connected to corresponding one of the gate lines;

a first semiconductor portion formed to be island-shaped and to overlap the gate electrode having a gate insulating film interposed therebetween;

a source electrode arranged to overlap the gate electrode having the gate insulating film and the first semiconductor portion interposed therebetween and connected to corresponding one of the source lines;

a drain electrode arranged to overlap the gate electrode having the gate insulating film and the first semiconductor portion interposed therebetween and connected to corresponding one of the pixel electrodes;

a second semiconductor portion formed to be island-shaped between the gate insulating film and the source electrode so as to overlap the gate electrode; and

a conductive portion arranged to overlap the gate electrode having the gate insulating film and the second semiconductor portion interposed therebetween,

the method comprising;

an inspecting step of detecting, out of the plurality of thin film transistors, a thin film transistor in which a short-circuit portion is formed by a short-circuit established at the source electrode and the drain electrode; and

a repairing step being carried out for the thin film transistor upon detection of the short-circuit portion in the inspecting step, by bringing the source line connected to the source electrode and the pixel electrode connected to the drain electrode into conduction by a switching element including the short-circuit portion, the second semiconductor portion and the conductive portion.

9. The method for manufacturing a thin film transistor array substrate of claim 8, wherein

the conductive portion is a bypass wiring arranged for each of the source lines per each of the intersections of the gate lines and the source lines, and extends along each of the source lines, and

in the repairing step, by subjecting the source line connected to the thin film transistor to laser radiation, a duplicately disposed portion of the source line with respect to the bypass wiring is separated.

10. The method for manufacturing a thin film transistor array substrate of claim 9, wherein

the gate electrode is structured with part of the corresponding one of the gate lines, and the corresponding one of the gate lines is provided with a slit formed around the source electrode and the drain electrode, and

in the repairing step, by subjecting an overlap portion between the source electrode and the gate line and an overlap portion between the drain electrode and the gate line in the thin film transistor to laser radiation, the source electrode and the gate line are connected each other, and the drain electrode and the gate line are connected to each other, and by subjecting a portion between the slit and a side edge of the gate line to laser radiation, the part of the gate line is separated.

11. The method for manufacturing a thin film transistor array substrate of claim 9, wherein

the gate electrode has a protrusion portion in which the corresponding one of the gate lines is protruding sideways,

the source electrode and the drain electrode are arranged so as to overlap the protrusion portion, and

in the repairing step, by subjecting a base portion of the protrusion portion in the thin film transistor to laser radiation, the protrusion portion is separated.

12. The method for manufacturing a thin film transistor array substrate of claim 8, wherein

the conductive portion is a floating electrode arranged per each of the intersections of the gate lines and the source lines, and extends along the source electrode,

the gate electrode is structured with part of the corresponding one of the gate lines, and the corresponding one of the gate lines is provided with a slit formed so as to cross the drain electrode and the floating electrode, and

in the repairing step, in the thin film transistor, by subjecting the drain electrode to laser radiation via the slit, the drain electrode is cut;

by subjecting a portion between the slit and a side edge of the gate line, the part of the gate line is separated; and

by subjecting an overlap portion between the separated gate line and the floating electrode and an overlap portion between the separated gate line and the drain electrode to laser radiation, the separated gate line and the floating electrode are connected to each other, and the separated gate line and the cut drain electrode are connected to each other.