SEMICONDUCTOR MEMORY DEVICE

• US 20100289084A1
• Filed: 05/11/2010
• Published: 11/18/2010
• Est. Priority Date: 05/15/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sim, Hyun Jun, Yoon, Hong Sik, Zhao, Jinshi, Baek, Ingyu, Park, Minyoung
• Granted Patent: US 8,264,018 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor

Abstract

Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.

Claims

1. A semiconductor memory device comprising:

a gate of a first wordline transistor disposed in a first region of a semiconductor substrate;

a gate of a bitline transistor disposed in a second region of the semiconductor substrate;

at least one first wordline channel pillar penetrating the gate of the first wordline transistor and insulated from the gate of the first wordline transistor;

at least one bitline channel pillar penetrating the gate of the bitline transistor and insulated from the gate of the bitline transistor;

a local bitline extending in a first direction substantially vertical to an upper surface of the semiconductor substrate and electrically connected to the bitline channel pillar;

a first local wordline disposed at one side of the local bitline, extending in a second direction substantially perpendicular to the first direction so as to intersect the local bitline, and electrically connected to the first wordline channel pillar; and

a first memory cell formed at an intersection between the local bitline and the first local wordline.

2. The semiconductor memory device of claim 1, wherein the gate of the bitline transistor is coupled to the gate of the first wordline transistor, such that the gate of the bitline transistor and the gate of the first wordline transistor are controlled by a single block selection signal.

3. The semiconductor memory device of claim 1, further comprising:

a gate of a bias transistor disposed in the first region;

at least one bias channel pillar penetrating the gate of the bias transistor and insulated from the gate of the bias transistor; and

a bias line coupled to the bias channel pillar.

4. The semiconductor memory device of claim 3, wherein the gate of the bias transistor is coupled to the gate of the first wordline transistor, and

the gate of the bitline transistor is electrically connected to the bias channel pillar.

5. The semiconductor memory device of claim 3, wherein the bias line is formed in a bias active portion defined in the semiconductor substrate below the gate of the bias transistor and the bias line is doped with dopants.

6. The semiconductor memory device of claim 1, wherein the at least one first wordline channel pillar and/or the at least one bitline channel pillar are substantially undoped.

7. The semiconductor memory device of claim 1, further comprising:

a gate of a second wordline transistor disposed in the first region;

at least one second wordline channel pillar penetrating the gate of the second wordline transistor and insulated from the gate of the second wordline transistor;

a second local wordline disposed at the other side of the local bitline in the second region, extending in the second direction to intersect the local bitline, and electrically connected to the second wordline channel pillar; and

a second memory cell formed at an intersection between the local bitline and the second local wordline,

wherein the gate of the first wordline transistor is coupled to the gate of the second wordline transistor.

8. The semiconductor memory device of claim 7, further comprising:

a first global wordline coupled to the first wordline channel pillar;

a second global wordline coupled to the second wordline channel pillar; and

a global bitline coupled to the bitline channel pillar.

9. The semiconductor memory device of claim 8, wherein the at least one first wordline channel pillar and/or the at least one bitline channel pillar are doped with a first dopant different from a second dopant in the first global wordline, the second global wordline and/or the global bitline.

10. The semiconductor memory device of claim 8, wherein the first global wordline is formed in a first wordline active portion defined in the semiconductor substrate below the gate of the first wordline transistor,

the second global wordline is formed in a second wordline active portion defined in the semiconductor substrate below the gate of the second wordline transistor, and

the global bitline is formed in a bitline active portion defined in the semiconductor substrate below the gate of the bitline transistor.

11. The semiconductor memory device of claim 7, wherein the first and second local wordlines are located at substantially the same level.

12. The semiconductor memory device of claim 7, wherein the first memory cell includes a first variable resistor interposed between the first local wordline and the local bitline.

13. The semiconductor memory device of claim 12, wherein

the second memory cell includes a second variable resistor interposed between the second local wordline and the local bitline.

14. The semiconductor memory device of claim 7, further comprising:

a gate of a block selection transistor disposed in the first region and spaced apart from the gates of the first and second wordline transistors;

at least one block selection channel pillar penetrating the gate of the block selection transistor and insulated from the gate of the block selection transistor; and

a block selection signal line electrically connected to the block selection channel pillar,

wherein the block selection channel pillar is electrically connected to the gates of the first and second wordline transistors, which are coupled to each other.

15. The semiconductor memory device of claim 7, wherein the first local wordline comprises a plurality of first local wordlines and the second local wordline comprises a plurality of second local wordlines,

wherein the first local wordlines are stacked on one side of the local bitline so as to be spaced apart from one another in the first direction,

wherein the second local wordlines are stacked on the other side of the local bitline so as to be spaced apart from one another in the first direction,

wherein the first wordline transistor comprises a plurality of first wordline transistors in the first region and the second wordline transistor comprises a plurality of second wordline transistors in the first region,

wherein the gates of the first wordline transistors and the gates of the second wordline transistors are alternately disposed along the second direction in the first region,

wherein each of the first local wordlines is electrically connected to the first wordline channel pillar penetrating the gate of the first wordline transistors,

wherein each of the second local wordlines is electrically connected to the second wordline channel pillar penetrating the gate of the second wordline transistors, and

wherein the gates of the first wordline transistors and the gates of the second wordline transistors are coupled to each other.

16. A semiconductor memory device comprising:

a gate of a wordline transistor disposed on a semiconductor substrate;

a gate of a bitline transistor disposed on the semiconductor substrate;

at least one wordline channel pillar penetrating the gate of the wordline transistor and insulated from the gate of the wordline transistor;

at least one bitline channel pillar penetrating the gate of the bitline transistor and insulated from the gate of the bitline transistor;

a local bitline extending in a first direction and electrically connected to the bitline channel pillar; and

a local wordline disposed at one side of the local bitline, extending in a second direction different from the first direction so as to intersect the local bitline, and electrically connected to the wordline channel pillar.

17. The semiconductor memory device of claim 16, wherein the local wordline extends in the second direction substantially perpendicular to the first direction.

18. A system comprising:

a semiconductor device comprising;

a gate of a wordline transistor disposed on a semiconductor substrate;

a gate of a bitline transistor disposed on the semiconductor substrate;

at least one wordline channel pillar penetrating the gate of the wordline transistor and insulated from the gate of the wordline transistor;

at least one bitline channel pillar penetrating the gate of the bitline transistor and insulated from the gate of the bitline transistor;

a local bitline extending in a first direction and electrically connected to the bitline channel pillar; and

a local wordline disposed at one side of the local bitline, extending in a second direction different from the first direction so as to intersect the local bitline, and electrically connected to the wordline channel pillar; and

a CPU or a controller coupled to the semiconductor device.