Magnetic Tunnel Junction Device and Fabrication

• US 20100289098A1
• Filed: 05/14/2009
• Published: 11/18/2010
• Est. Priority Date: 05/14/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhu, Xiaochun, Kang, Seung H., Li, Xia
• Granted Patent: US 8,455,267 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) device on a structure that includes a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device including a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis.

Claims

1. A method comprising:

forming a magnetic tunnel junction (MTJ) device on a structure that comprises a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device comprising a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis;

forming and planarizing an insulating layer above the logic cap layer; and

performing a copper damascene process to open a top trench in the insulating layer, to open a top via to the top electrode, to open a logic via to metal in the bottom metal-filled trench, or to open the top via and the logic via, to deposit copper in the top trench and in the top via, in the logic via, or in the top via and in the logic via, and to perform a copper chemical mechanical planarization of the deposited copper.

2. The method of claim 1, wherein the offset of the MTJ axis from the normal axis is greater than a width of the magnetic tunnel junction layers.

3. The method of claim 1, wherein the bottom metal-filled trench is substantially filled with copper.

4. The method of claim 1, wherein the bottom metal-filled trench forms a copper pad, and wherein at least a portion of the bottom electrode is formed on the copper pad.

5. The method of claim 4, wherein the magnetic tunnel junction layers are not above the copper pad.

6. The method of claim 1, wherein the top via and the logic via are formed in a common process stage.

7. The method of claim 1, wherein an easy axis magnetic tunnel junction magnetic anneal of at least one of the magnetic tunnel junction layers aligns a magnetic field orientation of the magnetic tunnel junction device.

8. The method of claim 1, wherein the bottom cap layer comprises silicon carbide or silicon nitride.

9. The method of claim 1, wherein the bottom cap layer is formed before the bottom metal-filled trench is formed.

10. The method of claim 1, wherein the magnetic tunnel junction seal layer comprises silicon nitride or silicon carbide.

11. The method of claim 1, wherein the bottom electrode comprises tantalum or tantalum nitride and wherein the top electrode comprises tantalum or tantalum nitride.

12. The method of claim 1, wherein the logic cap layer comprises silicon carbide or silicon nitride.

13. The method of claim 1, wherein a height of the top via is adjustable.

14. An apparatus comprising:

a semiconductor device formed by the method of claim 1.

15. The apparatus of claim 14, integrated in at least one semiconductor die.

16. The apparatus of claim 14, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the semiconductor device is integrated.

17. An apparatus comprising:

a structure that comprises a bottom cap layer surrounding a metal pad; and

a magnetic tunnel junction (MTJ) device comprising a bottom electrode coupled to the structure, the MTJ device comprising magnetic tunnel junction layers, a top electrode, and a logic cap layer, wherein the MTJ device is offset with respect to the metal pad.

18. The apparatus of claim 17, wherein the offset defines a distance in a direction parallel to a surface of the metal pad.

19. The apparatus of claim 17, wherein an easy axis magnetic tunnel junction magnetic anneal of at least one of the magnetic tunnel junction layers aligns a magnetic field orientation of the magnetic tunnel junction device.

20. The apparatus of claim 17, wherein the bottom cap layer comprises silicon carbide or silicon nitride.

21. The apparatus of claim 17, wherein the bottom electrode comprises at least one of tantalum and tantalum nitride.

22. The apparatus of claim 17, wherein the top electrode comprises at least one of tantalum and tantalum nitride.

23. The apparatus of claim 17, wherein the logic cap layer comprises silicon carbide or silicon nitride.

24. The apparatus of claim 17, integrated in at least one semiconductor die.

25. The apparatus of claim 24, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the at least one semiconductor die is integrated.

26. A method comprising:

forming a first insulating layer above a substrate;

forming a bottom cap layer above the first insulating layer;

performing a first copper damascene process to open bottom trenches and bottom vias in the first insulating layer, to plate copper in the bottom trenches and in the bottom vias, and to perform a copper chemical mechanical planarization, the copper-filled bottom trenches each having a normal axis;

forming a bottom electrode above the bottom cap layer and above the copper-filled bottom trenches;

forming magnetic tunnel junction layers above the bottom electrode;

forming a hardmask above the magnetic tunnel junction layers;

patterning magnetic tunnel junction (MTJ) structures each having an MTJ axis that is offset from the normal axis of an adjacent copper-filled bottom trench;

forming a magnetic tunnel junction seal layer above and adjacent to the magnetic tunnel junction structures and above the bottom electrode;

forming a second insulating layer above the magnetic tunnel junction seal layer;

planarizing the second insulating layer and opening tops of the magnetic tunnel junction structures;

forming a top electrode above the planarized second insulating layer and above the tops of the magnetic tunnel junction structures;

patterning the top electrode and the bottom electrode;

forming a logic cap layer above the bottom cap layer, the logic cap layer adjacent to the magnetic tunnel junction seal layer, adjacent to the second insulating layer, and above the patterned top electrode;

forming and planarizing a third insulating layer above the logic cap layer; and

performing a second copper damascene process to open at least one of a top via to the patterned top electrode and a logic via to one of the copper-filled bottom trenches and to open a top trench in the third insulating layer, to plate copper in the top trench and in the at least one of the top via and the logic via, and to perform a copper chemical mechanical planarization.

27. The method of claim 26, further comprising forming a final cap layer above the copper in the top metal trench and above the third insulating layer.

28. A method comprising:

a first step for forming a magnetic tunnel junction (MTJ) device on a structure that comprises a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device comprising a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis;

a second step for forming and planarizing an insulating layer above the logic cap layer; and

a third step for performing a copper damascene process to open a top trench in the insulating layer, to open a top via to the top electrode, to open a logic via to metal in the bottom metal-filled trench, or to open the top via and the logic via, to deposit copper in the top trench and in the top via, in the logic via, or in the top via and in the logic via, and to perform a copper chemical mechanical planarization of the deposited copper.

29. A method comprising:

receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising;

a structure that comprises a bottom cap layer surrounding a metal pad; and

a magnetic tunnel junction (MTJ) device comprising a bottom electrode coupled to the structure, the MTJ device comprising magnetic tunnel junction layers, a top electrode, and a logic cap layer, wherein the MTJ device is offset with respect to the metal pad;

transforming the design information to comply with a file format; and

generating a data file comprising the transformed design information.

30. The method of claim 29, wherein the data file comprises a GDSII format.

31. A method comprising:

receiving a data file comprising design information corresponding to a semiconductor device; and

fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises;

a structure that comprises a bottom cap layer surrounding a metal pad; and

a magnetic tunnel junction (MTJ) device comprising a bottom electrode coupled to the structure, the MTJ device comprising magnetic tunnel junction layers, a top electrode, and a logic cap layer, wherein the MTJ device is offset with respect to the metal pad.

32. The method of claim 31, wherein the data file has a GDSII format.

33. A method comprising:

receiving design information comprising physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device comprising a semiconductor structure comprising;

a structure that comprises a bottom cap layer surrounding a metal pad; and

a magnetic tunnel junction (MTJ) device comprising a bottom electrode coupled to the structure, the MTJ device comprising magnetic tunnel junction layers, a top electrode, and a logic cap layer, wherein the MTJ device is offset with respect to the metal pad; and

transforming the design information to generate a data file.

34. The method of claim 33, wherein the data file has a GERBER format.

35. A method comprising:

receiving a data file comprising design information comprising physical positioning information of a packaged semiconductor device on a circuit board; and

manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises a semiconductor structure comprising;

a structure that comprises a bottom cap layer surrounding a metal pad; and

a magnetic tunnel junction (MTJ) device comprising a bottom electrode coupled to the structure, the MTJ device comprising magnetic tunnel junction layers, a top electrode, and a logic cap layer, wherein the MTJ device is offset with respect to the metal pad.

36. The method of claim 35, wherein the data file has a GERBER format.

37. The method of claim 35, further comprising integrating the circuit board into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

38. An apparatus comprising:

means for initiating formation of a magnetic tunnel junction (MTJ) device on a structure that comprises a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device comprising a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis;

means for initiating formation and planarization of an insulating layer above the logic cap layer; and

means for initiating a copper damascene process to open a top trench in the insulating layer, to open a top via to the top electrode, to open a logic via to metal in the bottom metal-filled trench, or to open the top via and the logic via, to deposit copper in the top trench and in the top via, in the logic via, or in the top via and in the logic via, and to perform a copper chemical mechanical planarization of the deposited copper.

39. The apparatus of claim 38, wherein the means for initiating formation of the MTJ device, the means for initiating formation and planarization of the insulating layer, and the means for initiating the copper damascene process are implemented at a processor integrated into an electronic device.

40. An apparatus comprising:

first protective means for protecting against formation of recesses in an insulating layer, the first protective means surrounding a metal pad; and

a magnetic tunnel junction (MTJ) device comprising;

means for coupling the MTJ device to the metal pad, wherein the MTJ device is offset with respect to the metal pad;

magnetic tunnel junction layers;

a top electrode; and

second protective means for sealing the MTJ device.

41. The apparatus of claim 40, integrated in at least one semiconductor die.

42. The apparatus of claim 41, further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the at least one semiconductor die is integrated.