CAPACITANCE INTERFACE CIRCUIT

• US 20100289555A1
• Filed: 07/30/2010
• Published: 11/18/2010
• Est. Priority Date: 04/07/2009
• Status: Active Grant

• Current Assignee: Ite Tech (ITE Technologies Incorporated)
• Original Assignee: Ite Tech (ITE Technologies Incorporated)
• Inventors: Cheng, Ping-Pao
• Granted Patent: US 8,237,489 B2
• Time in Patent Office: Days
• US Class Current: 327/524
• CPC Class Codes: G01D 5/24 by varying capacitance

Abstract

A capacitance interface circuit is provided. An external inductive capacitor is divided into a variable portion and an invariable portion. The capacitance of an internal adjustable capacitor is designed to be equal or close to the fixed capacitance of the external inductive capacitor. The internal adjustable capacitor is used for storing charges having a polarity opposite to that of the invariable portion of the external inductive capacitor in order to neutralize the effect of the invariable portion of the external inductive capacitor. Thus, a charge converter composed of a fully-differential amplifier and feedback capacitors needs only work on the variable portion of the external inductive capacitor, and accordingly the accuracy in subsequent data processing is increased.

Claims

1. A capacitance interface circuit, comprising:

a first switch, having a first terminal for receiving a positive reference voltage and a control terminal for receiving a first control signal;

a second switch, having a first terminal for receiving a negative reference voltage, a second terminal coupled to a second terminal of the first switch, and a control terminal for receiving a second control signal;

a first capacitor, having a first terminal coupled to the second terminal of the second switch, wherein the first capacitor has a variable portion and an invariable portion;

a third switch, having a first terminal coupled to a second terminal of the first capacitor and a control terminal for receiving the first control signal;

a fourth switch, having a first terminal coupled to the second terminal of the first capacitor and a control terminal for receiving the second control signal;

a fully-differential amplifier, having a positive input terminal coupled to a second terminal of the third switch and a negative input terminal coupled to a second terminal of the fourth switch;

a first feedback capacitor, having a first terminal coupled to the second terminal of the third switch and a second terminal coupled to a negative output terminal of the fully-differential amplifier;

a second feedback capacitor, having a first terminal coupled to the second terminal of the fourth switch and a second terminal coupled to a positive output terminal of the fully-differential amplifier; and

a cancellation means, for cancelling the invariable portion.

2. A capacitance interface circuit, comprising:

a first switch, having a first terminal for receiving a positive reference voltage and a control terminal for receiving a first control signal;

a second switch, having a first terminal for receiving a negative reference voltage, a second terminal coupled to a second terminal of the first switch, and a control terminal for receiving a second control signal;

a first capacitor, having a first terminal coupled to the second terminal of the second switch;

a third switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the second control signal;

a fourth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the third switch, and a control terminal for receiving the first control signal;

a second capacitor, having a first terminal coupled to the second terminal of the fourth switch;

a fifth switch, having a first terminal coupled to a second terminal of the first capacitor and a control terminal for receiving the first control signal;

a sixth switch, having a first terminal coupled to the second terminal of the first capacitor and a control terminal for receiving the second control signal;

a seventh switch, having a first terminal coupled to a second terminal of the second capacitor and a control terminal for receiving the first control signal;

an eighth switch, having a first terminal coupled to the second terminal of the second capacitor and a control terminal for receiving the second control signal;

a fully-differential amplifier, having a positive input terminal coupled to second terminals of the fifth switch and the seventh switch and a negative input terminal coupled to second terminals of the sixth switch and the eighth switch;

a first feedback capacitor, having a first terminal coupled to the second terminal of the fifth switch and a second terminal coupled to a negative output terminal of the fully-differential amplifier; and

a second feedback capacitor, having a first terminal coupled to the second terminal of the sixth switch and a second terminal coupled to a positive output terminal of the fully-differential amplifier.

3. The capacitance interface circuit according to claim 2, wherein the first control signal and the second control signal have a phase difference of 180°

.

4. The capacitance interface circuit according to claim 2, wherein the first capacitor and the second capacitor are respectively an external inductive capacitor of the capacitance interface circuit.

5. The capacitance interface circuit according to claim 2, wherein the first capacitor is a first external inductive capacitor of the capacitance interface circuit, the second capacitor is a first internal adjustable capacitor of the capacitance interface circuit, a capacitance of the first capacitor comprises a first fixed capacitance and a first variable capacitance, and a capacitance of the second capacitor is substantially equal to the first fixed capacitance.

6. A capacitance interface circuit, comprising:

a first switch, having a first terminal for receiving a positive reference voltage and a control terminal for receiving a first control signal;

a second switch, having a first terminal for receiving a negative reference voltage, a second terminal coupled to a second terminal of the first switch, and a control terminal for receiving a second control signal;

a first capacitor, having a first terminal coupled to the second terminal of the second switch;

a third switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the first control signal;

a fourth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the third switch, and a control terminal for receiving the second control signal;

a second capacitor, having a first terminal coupled to the second terminal of the fourth switch;

a fifth switch, having a first terminal coupled to a second terminal of the first capacitor and a control terminal for receiving the first control signal;

a sixth switch, having a first terminal coupled to the second terminal of the first capacitor and a control terminal for receiving the second control signal;

a seventh switch, having a first terminal coupled to a second terminal of the second capacitor and a control terminal for receiving the first control signal;

an eighth switch, having a first terminal coupled to the second terminal of the second capacitor and a control terminal for receiving the second control signal;

a fully-differential amplifier, having a positive input terminal coupled to second terminals of the fifth switch and the eighth switch and a negative input terminal coupled to second terminals of the sixth switch and the seventh switch;

a first feedback capacitor, having a first terminal coupled to the second terminal of the fifth switch and a second terminal coupled to a negative output terminal of the fully-differential amplifier; and

a second feedback capacitor, having a first terminal coupled to the second terminal of the sixth switch and a second terminal coupled to a positive output terminal of the fully-differential amplifier.

7. The capacitance interface circuit according to claim 6, wherein the first control signal and the second control signal have a phase difference of 180°

.

8. The capacitance interface circuit according to claim 6, wherein the first capacitor and the second capacitor are respectively an external inductive capacitor of the capacitance interface circuit.

9. The capacitance interface circuit according to claim 6, wherein the first capacitor is a first external inductive capacitor of the capacitance interface circuit, the second capacitor is a first internal adjustable capacitor of the capacitance interface circuit, a capacitance of the first capacitor comprises a first fixed capacitance and a first variable capacitance, and a capacitance of the second capacitor is substantially equal to the first fixed capacitance.

10. A capacitance interface circuit, comprising:

a first switch, having a first terminal for receiving a positive reference voltage and a control terminal for receiving a first control signal;

a second switch, having a first terminal for receiving a negative reference voltage, a second terminal coupled to a second terminal of the first switch, and a control terminal for receiving a second control signal;

a first capacitor, having a first terminal coupled to the second terminal of the second switch;

a third switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the first control signal;

a fourth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the third switch, and a control terminal for receiving the second control signal;

a second capacitor, having a first terminal coupled to the second terminal of the fourth switch;

a fifth switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the second control signal;

a sixth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the fifth switch, and a control terminal for receiving the first control signal;

a third capacitor, having a first terminal coupled to the second terminal of the sixth switch;

a seventh switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the first control signal;

an eighth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the seventh switch, and a control terminal for receiving the second control signal;

a fourth capacitor, having a first terminal coupled to the second terminal of the eighth switch;

a ninth switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the first control signal;

a tenth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the ninth switch, and a control terminal for receiving the second control signal;

a fifth capacitor, having a first terminal coupled to the second terminal of the tenth switch;

a eleventh switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the second control signal;

a twelfth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the eleventh switch, and a control terminal for receiving the first control signal;

a sixth capacitor, having a first terminal coupled to the second terminal of the twelfth switch;

a thirteenth switch, having a first terminal coupled to a second terminal of the first capacitor and a control terminal for receiving the first control signal;

a fourteenth switch, having a first terminal coupled to the second terminal of the first capacitor and a control terminal for receiving the second control signal;

a fifteenth switch, having a first terminal coupled to a second terminal of the second capacitor and a control terminal for receiving the first control signal;

a sixteenth switch, having a first terminal coupled to the second terminal of the second capacitor and a control terminal for receiving the second control signal;

a seventeenth switch, having a first terminal coupled to a second terminal of the third capacitor and a control terminal for receiving the first control signal;

an eighteenth switch, having a first terminal coupled to the second terminal of the third capacitor and a control terminal for receiving the second control signal;

a nineteenth switch, having a first terminal coupled to a second terminal of the fourth capacitor and a control terminal for receiving the first control signal;

a twentieth switch, having a first terminal coupled to the second terminal of the fourth capacitor and a control terminal for receiving the second control signal;

a twenty first switch, having a first terminal coupled to a second terminal of the fifth capacitor and a control terminal for receiving the first control signal;

a twenty second switch, having a first terminal coupled to the second terminal of the fifth capacitor and a control terminal for receiving the second control signal;

a twenty third switch, having a first terminal coupled to a second terminal of the sixth capacitor and a control terminal for receiving the first control signal;

a twenty fourth switch, having a first terminal coupled to the second terminal of the sixth capacitor and a control terminal for receiving the second control signal;

a fully-differential amplifier, having a positive input terminal coupled to second terminals of the thirteenth switch, the fifteenth switch, the seventeenth switch, the twentieth switch, the twenty second switch, and the twenty fourth switch, and a negative input terminal coupled to second terminals of the fourteenth switch, the sixteenth switch, the eighteenth switch, the nineteenth switch, the twenty first switch, and the twenty third switch;

a first feedback capacitor, having a first terminal coupled to the positive input terminal of the fully-differential amplifier and a second terminal coupled to a negative output terminal of the fully-differential amplifier; and

a second feedback capacitor, having a first terminal coupled to the negative input terminal of the fully-differential amplifier and a second terminal coupled to a positive output terminal of the fully-differential amplifier.

11. The capacitance interface circuit according to claim 10, wherein the first control signal and the second control signal have a phase difference of 180°

.

12. The capacitance interface circuit according to claim 10, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are respectively an external inductive capacitor of the capacitance interface circuit.

13. The capacitance interface circuit according to claim 10, wherein the first capacitor is a first external inductive capacitor of the capacitance interface circuit, the second capacitor is a second external inductive capacitor of the capacitance interface circuit, the third capacitor is a first internal adjustable capacitor of the capacitance interface circuit, the fourth capacitor is a third external inductive capacitor of the capacitance interface circuit, the fifth capacitor is a fourth external inductive capacitor of the capacitance interface circuit, the sixth capacitor is a second internal adjustable capacitor of the capacitance interface circuit, a capacitance of the first capacitor comprises a first fixed capacitance and a first variable capacitance, a capacitance of the second capacitor comprises a second fixed capacitance and a second variable capacitance, and a capacitance of the third capacitor is substantially equal to a sum of the first fixed capacitance and the second fixed capacitance, a capacitance of the fourth capacitor comprises a third fixed capacitance and a third variable capacitance, a capacitance of the fifth capacitor comprises a fourth fixed capacitance and a fourth variable capacitance, and a capacitance of the sixth capacitor is substantially equal to a sum of the third fixed capacitance and the fourth fixed capacitance.

14. A capacitance interface circuit, comprising:

a first switch, having a first terminal for receiving a positive reference voltage and a control terminal for receiving a first control signal;

a second switch, having a first terminal for receiving a negative reference voltage, a second terminal coupled to a second terminal of the first switch, and a control terminal for receiving a second control signal;

a first capacitor, having a first terminal coupled to the second terminal of the second switch, wherein the first capacitor has a variable portion and an invariable portion;

a third switch, having a first terminal coupled to a second terminal of the first capacitor and a control terminal for receiving a third control signal;

a fourth switch, having a first terminal coupled to the second terminal of the first capacitor and a control terminal for receiving a fourth control signal;

a fully-differential amplifier, having a positive input terminal coupled to a second terminal of the third switch, a negative input terminal coupled to a second terminal of the fourth switch, and a common mode receiving terminal for receiving a common mode voltage;

a first feedback capacitor, having a first terminal coupled to the second terminal of the third switch and a second terminal coupled to a negative output terminal of the fully-differential amplifier;

a second feedback capacitor, having a first terminal coupled to the second terminal of the fourth switch and a second terminal coupled to a positive output terminal of the fully-differential amplifier;

a fifth switch, having a first terminal coupled to the second terminal of the first capacitor, a control terminal for receiving a fifth control signal, and a second terminal coupled to the common mode voltage; and

a cancellation means, for cancelling the invariable portion.

15. A capacitance interface circuit, comprising:

a first switch, having a first terminal for receiving a positive reference voltage and a control terminal for receiving a first control signal;

a second switch, having a first terminal for receiving a negative reference voltage, a second terminal coupled to a second terminal of the first switch, and a control terminal for receiving a second control signal;

a first capacitor, having a first terminal coupled to the second terminal of the second switch;

a third switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the second control signal;

a fourth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the third switch, and a control terminal for receiving the first control signal;

a second capacitor, having a first terminal coupled to the second terminal of the fourth switch;

a fifth switch, having a first terminal coupled to a second terminal of the first capacitor and a control terminal for receiving a third control signal;

a sixth switch, having a first terminal coupled to the second terminal of the first capacitor and a control terminal for receiving a fourth control signal;

a seventh switch, having a first terminal coupled to a second terminal of the second capacitor and a control terminal for receiving the third control signal;

an eighth switch, having a first terminal coupled to the second terminal of the second capacitor and a control terminal for receiving the fourth control signal;

a fully-differential amplifier, having a positive input terminal coupled to second terminals of the fifth switch and the seventh switch, a negative input terminal coupled to second terminals of the sixth switch and the eighth switch, and a common mode receiving terminal for receiving a common mode voltage;

a first feedback capacitor, having a first terminal coupled to the second terminal of the fifth switch and a second terminal coupled to a negative output terminal of the fully-differential amplifier;

a second feedback capacitor, having a first terminal coupled to the second terminal of the sixth switch and a second terminal coupled to a positive output terminal of the fully-differential amplifier;

a ninth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving a fifth control signal, and a second terminal coupled to the second terminal of the first capacitor; and

a tenth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving the fifth control signal, and a second terminal coupled to the second terminal of the second capacitor.

16. The capacitance interface circuit according to claim 15, wherein the first control signal and the second control signal have a phase difference of 180°

, duty cycles of the first control signal and the second control signal are 50%, a cycle of the fifth control signal is half of a cycle of the second control signal, a cycle of the third control signal is the same as a cycle of the first control signal, a duty cycle of the third control signal is 25%, a cycle of the fourth control signal is the same as the cycle of the second control signal, and a duty cycle of the fourth control signal is 25%.

17. The capacitance interface circuit according to claim 15, wherein the first capacitor and the second capacitor are respectively an external inductive capacitor of the capacitance interface circuit.

18. The capacitance interface circuit according to claim 15, wherein the first capacitor is a first external inductive capacitor of the capacitance interface circuit, the second capacitor is a first internal adjustable capacitor of the capacitance interface circuit, a capacitance of the first capacitor comprises a first fixed capacitance and a first variable capacitance, and a capacitance of the second capacitor is substantially equal to the first fixed capacitance.

19. A capacitance interface circuit, comprising:

a first switch, having a first terminal for receiving a positive reference voltage and a control terminal for receiving a first control signal;

a second switch, having a first terminal for receiving a negative reference voltage, a second terminal coupled to a second terminal of the first switch, and a control terminal for receiving a second control signal;

a first capacitor, having a first terminal coupled to the second terminal of the second switch;

a third switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the first control signal;

a fourth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the third switch, and a control terminal for receiving the second control signal;

a second capacitor, having a first terminal coupled to the second terminal of the fourth switch;

a fifth switch, having a first terminal coupled to a second terminal of the first capacitor and a control terminal for receiving a third control signal;

a sixth switch, having a first terminal coupled to the second terminal of the first capacitor and a control terminal for receiving a fourth control signal;

a seventh switch, having a first terminal coupled to a second terminal of the second capacitor and a control terminal for receiving the third control signal;

an eighth switch, having a first terminal coupled to a second terminal of the second capacitor and a control terminal for receiving the fourth control signal;

a fully-differential amplifier, having a positive input terminal coupled to second terminals of the fifth switch and the eighth switch, a negative input terminal coupled to second terminals of the sixth switch and the seventh switch, and a common mode receiving terminal for receiving a common mode voltage;

a first feedback capacitor, having a first terminal coupled to the second terminal of the fifth switch and a second terminal coupled to a negative output terminal of the fully-differential amplifier;

a second feedback capacitor, having a first terminal coupled to the second terminal of the sixth switch and a second terminal coupled to a positive output terminal of the fully-differential amplifier;

a ninth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving a fifth control signal, and a second terminal coupled to the second terminal of the first capacitor; and

a tenth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving the fifth control signal, and a second terminal coupled to the second terminal of the second capacitor.

20. The capacitance interface circuit according to claim 19, wherein the first control signal and the second control signal have a phase difference of 180°

, duty cycles of the first control signal and the second control signal are 50%, a cycle of the fifth control signal is half of a cycle of the second control signal, a cycle of the third control signal is the same as a cycle of the first control signal, a duty cycle of the third control signal is 25%, a cycle of the fourth control signal is the same as the cycle of the second control signal, and a duty cycle of the fourth control signal is 25%.

21. The capacitance interface circuit according to claim 19, wherein the first capacitor and the second capacitor are respectively an external inductive capacitor of the capacitance interface circuit.

22. The capacitance interface circuit according to claim 19, wherein the first capacitor is a first external inductive capacitor of the capacitance interface circuit, the second capacitor is a first internal adjustable capacitor of the capacitance interface circuit, a capacitance of the first capacitor comprises a first fixed capacitance and a first variable capacitance, and a capacitance of the second capacitor is substantially equal to the first fixed capacitance.

23. A capacitance interface circuit, comprising:

a first switch, having a first terminal for receiving a positive reference voltage and a control terminal for receiving a first control signal;

a second switch, having a first terminal for receiving a negative reference voltage, a second terminal coupled to a second terminal of the first switch, and a control terminal for receiving a second control signal;

a first capacitor, having a first terminal coupled to the second terminal of the second switch;

a third switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the first control signal;

a fourth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the third switch, and a control terminal for receiving the second control signal;

a second capacitor, having a first terminal coupled to the second terminal of the fourth switch;

a fifth switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the second control signal;

a sixth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the fifth switch, and a control terminal for receiving the first control signal;

a third capacitor, having a first terminal coupled to the second terminal of the sixth switch;

a seventh switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the first control signal;

an eighth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the seventh switch, and a control terminal for receiving the second control signal;

a fourth capacitor, having a first terminal coupled to the second terminal of the eighth switch;

a ninth switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the first control signal;

a tenth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the ninth switch, and a control terminal for receiving the second control signal;

a fifth capacitor, having a first terminal coupled to the second terminal of the tenth switch;

a eleventh switch, having a first terminal for receiving the positive reference voltage and a control terminal for receiving the second control signal;

a twelfth switch, having a first terminal for receiving the negative reference voltage, a second terminal coupled to a second terminal of the eleventh switch, and a control terminal for receiving the first control signal;

a sixth capacitor, having a first terminal coupled to the second terminal of the twelfth switch;

a thirteenth switch, having a first terminal coupled to a second terminal of the first capacitor and a control terminal for receiving a third control signal;

a fourteenth switch, having a first terminal coupled to the second terminal of the first capacitor and a control terminal for receiving a fourth control signal;

a fifteenth switch, having a first terminal coupled to a second terminal of the second capacitor and a control terminal for receiving the third control signal;

a sixteenth switch, having a first terminal coupled to the second terminal of the second capacitor and a control terminal for receiving the fourth control signal;

a seventeenth switch, having a first terminal coupled to a second terminal of the third capacitor and a control terminal for receiving the third control signal;

an eighteenth switch, having a first terminal coupled to the second terminal of the third capacitor and a control terminal for receiving the fourth control signal;

a nineteenth switch, having a first terminal coupled to a second terminal of the fourth capacitor and a control terminal for receiving the third control signal;

a twentieth switch, having a first terminal coupled to the second terminal of the fourth capacitor and a control terminal for receiving the fourth control signal;

a twenty first switch, having a first terminal coupled to a second terminal of the fifth capacitor and a control terminal for receiving the third control signal;

a twenty second switch, having a first terminal coupled to the second terminal of the fifth capacitor and a control terminal for receiving the fourth control signal;

a twenty third switch, having a first terminal coupled to a second terminal of the sixth capacitor and a control terminal for receiving the third control signal;

a twenty fourth switch, having a first terminal coupled to the second terminal of the sixth capacitor and a control terminal for receiving the fourth control signal;

a fully-differential amplifier, having a positive input terminal coupled to second terminals of the thirteenth switch, the fifteenth switch, the seventeenth switch, the twentieth switch, the twenty second switch, and the twenty fourth switch, a negative input terminal coupled to second terminals of the fourteenth switch, the sixteenth switch, the eighteenth switch, the nineteenth switch, the twenty first switch, and the twenty third switch, and a common mode receiving terminal for receiving a common mode voltage;

a first feedback capacitor, having a first terminal coupled to the positive input terminal of the fully-differential amplifier and a second terminal coupled to a negative output terminal of the fully-differential amplifier;

a second feedback capacitor, having a first terminal coupled to the negative input terminal of the fully-differential amplifier and a second terminal coupled to a positive output terminal of the fully-differential amplifier;

a twenty fifth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving a fifth control signal, and a second terminal coupled to the second terminal of the first capacitor;

a twenty sixth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving the fifth control signal, and a second terminal coupled to the second terminal of the second capacitor;

a twenty seventh switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving the fifth control signal, and a second terminal coupled to the second terminal of the third capacitor;

a twenty eighth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving the fifth control signal, and a second terminal coupled to the second terminal of the fourth capacitor;

a twenty ninth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving the fifth control signal, and a second terminal coupled to the second terminal of the fifth capacitor; and

a thirtieth switch, having a first terminal for receiving the common mode voltage, a control terminal for receiving the fifth control signal, and a second terminal coupled to the second terminal of the sixth capacitor.

24. The capacitance interface circuit according to claim 23, wherein the first control signal and the second control signal have a phase difference of 180°

, duty cycles of the first control signal and the second control signal are 50%, a cycle of the fifth control signal is half of a cycle of the second control signal, a cycle of the third control signal is the same as a cycle of the first control signal, a duty cycle of the third control signal is 25%, a cycle of the fourth control signal is the same as the cycle of the second control signal, and a duty cycle of the fourth control signal is 25%.

25. The capacitance interface circuit according to claim 23, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are respectively an external inductive capacitor of the capacitance interface circuit.

26. The capacitance interface circuit according to claim 23, wherein the first capacitor is a first external inductive capacitor of the capacitance interface circuit, the second capacitor is a second external inductive capacitor of the capacitance interface circuit, the third capacitor is a first internal adjustable capacitor of the capacitance interface circuit, the fourth capacitor is a third external inductive capacitor of the capacitance interface circuit, the fifth capacitor is a fourth external inductive capacitor of the capacitance interface circuit, the sixth capacitor is a second internal adjustable capacitor of the capacitance interface circuit, a capacitance of the first capacitor comprises a first fixed capacitance and a first variable capacitance, a capacitance of the second capacitor comprises a second fixed capacitance and a second variable capacitance, a capacitance of the third capacitor is substantially equal to a sum of the first fixed capacitance and the second fixed capacitance, a capacitance of the fourth capacitor comprises a third fixed capacitance and a third variable capacitance, a capacitance of the fifth capacitor comprises a fourth fixed capacitance and a fourth variable capacitance, and a capacitance of the sixth capacitor is substantially equal to a sum of the third fixed capacitance and the fourth fixed capacitance.