PROCESSING METHOD FOR PROVIDING, STARTING FROM SIGNALS ACQUIRED BY A SET OF SENSORS, AN AGGREGATE SIGNAL AND DATA ACQUISITION SYSTEM USING SUCH METHOD

• US 20100289628A1
• Filed: 07/27/2010
• Published: 11/18/2010
• Est. Priority Date: 04/12/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pappalardo, Francesco, Visalli, Giuseppe
• Granted Patent: US 8,817,935 B2
• Time in Patent Office: Days
• US Class Current: 340/286.02
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W

Abstract

Embodiment for forming an aggregate signal from a plurality of starting signals, comprising:

• • acquiring said starting signals through respective sensors of a homogeneous sensors group;
  • converting acquired signals in respective digital signals having data represented with a predetermined bits number;
  • processing the digital signals to form aggregate signal.

The processing step comprises the operations of:

• • modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data;
  • forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.

Claims

1-18. -18. (canceled)

19. An encoder, comprising:

a first node operable to receive a first digital word that includes symbols in respective symbol positions within the first word;

a second node operable to receive a second digital word that includes symbols in respective symbol positions within the second word; and

an aggregator circuit coupled to the first and second nodes and operable to generate an aggregate word by logically combining each symbol within the first word with a symbol in a respective position within the second word.

20. The encoder of claim 19 wherein the first and second nodes comprise a same node.

21. The encoder of claim 19 wherein:

each symbol comprises a respective bit; and

each symbol position comprises a respective bit position.

22. The encoder of claim 19 wherein the aggregator circuit is operable to logically combine each symbol within the first word with a symbol in a same position within the second word.

23. The encoder of claim 19 wherein the aggregator circuit is operable to change for each symbol within the first word the respective position within the second word.

24. The encoder of claim 19 wherein the aggregator circuit is operable to change for each symbol within the first word the respective position within the second word in response to a signal from a source remote from the circuit and the first and second sensors.

25. The encoder of claim 19 wherein the aggregator circuit is further operable to:

receive first and second patterns from a source remote from the aggregator circuit and the first and second sensors;

change the positions of the two symbols within the first word according to the first pattern; and

change the positions of the two symbols within the second word according to the second pattern.

26. The encoder of claim 19 wherein the aggregator circuit comprises a processor.

27-31. -31. (canceled)

32. A system, comprising:

a first device operable to generate a first digital word that includes symbols in respective symbol positions within the first word;

a second device operable to generate a second digital word that includes symbols in respective symbol positions within the second word; and

an aggregator circuit coupled to the first and second devices and operable to generate an aggregate word by logically combining each symbol within the first word with a symbol in a respective position within the second word.

33. The system of claim 32 wherein:

the first device comprises a first sensor operable to generate the first digital word in response to a first stimulus; and

the second device comprises a second sensor operable to generate the second digital word in response to a second stimulus.

34. The system of claim 33 wherein the first stimulus is the same as the second stimulus.

35. The system of claim 33 wherein:

the first sensor comprises,

a first sensor element operable to generate in response to the first stimulus a first analog signal, and

a first converter coupled to the first sensor element and operable to convert the first analog signal into the first digital signal; and

the second sensor comprises,

a second sensor element operable to generate in response to the second stimulus a second analog signal, and

a second converter coupled to the second sensor element and operable to convert the second analog signal into the second digital signal.

36. The system of claim 32 wherein the first and second devices and the aggregator circuit are disposed on a same integrated circuit.

37. The system of claim 32 wherein the first and second devices and the aggregator circuit are disposed on at least two integrated circuits.

38. The system of claim 32, further comprising a controller coupled the aggregator circuit.

39. The system of claim 32 wherein the first and second devices, the aggregator circuit, and the controller are disposed on a same integrated circuit.

40. The system of claim 32 wherein the first and second devices, the aggregator circuit, and the controller are disposed on at least two integrated circuits.

41-43. -43. (canceled)

44. A method, comprising:

receiving a first digital word that includes symbols in respective symbol positions within the first word;

receiving a second digital word that includes symbols in respective symbol positions within the second word; and

generating an aggregate word by logically combining each symbol within the first word with a symbol in a respective position within the second word.

45. The method of claim 44 wherein generating the aggregate word comprises performing an exclusive or of each symbol within the first word with a symbol in a respective position within the second word.

46-47. -47. (canceled)