SYSTEM-IN PACKAGES

• US 20100290191A1
• Filed: 05/13/2010
• Published: 11/18/2010
• Est. Priority Date: 05/14/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Granted Patent: US 8,164,171 B2
• Time in Patent Office: Days
• US Class Current: 361/704
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

System-in packages, or multichip modules, are described which can include multi-layer chips in a multi-layer polymer structure, on-chip metal bumps on the multi-layer chips, intra-chip metal bumps in the multi-layer polymer structure, and patterned metal layers in the multi-layer polymer structure. The multi-layer chips in the multi-layer polymer structure can be connected to each other or to an external circuit through the on-chip metal bumps, the intra-chip metal bumps and the patterned metal layers. The system-in packages can be connected to external circuits through solder bumps, meal bumps or wirebonded wires.

Claims

1. A system-in package comprising:

a first polymer layer;

a first chip in the first polymer layer;

a first metal layer over the first chip and over a top surface of the first polymer layer, wherein the first metal layer is connected to the first chip;

a second polymer layer over the first polymer layer, over the first chip and over the first metal layer;

a second chip in the second polymer layer, wherein the second chip comprises a first metal bump in the second polymer layer;

a second metal bump in the second polymer layer and over the first metal layer, wherein the second metal bump is connected to the first metal layer, wherein the second metal bump is higher than the first metal bump, wherein a top surface of the first metal bump and a top surface of the second metal bump are not covered by the second polymer layer; and

a second metal layer on the top surface of the first metal bump, on the top surface of the second metal bump and over a top surface of the second polymer layer, wherein the second metal layer connects the first metal bump to the second metal bump, wherein the first metal bump is connected to the first chip through, in sequence, the second metal layer, the second metal bump and the first metal layer.

2. The system-in package of claim 1, wherein the first chip comprises a central-processing-unit (CPU) chip, a baseband chip, a graphics-processing-unit (GPU) chip, a digital-signal-processing (DSP) chip, a wireless local area network (WLAN) chip, a memory chip, a flash memory chip, a dynamic-random-access-memory (DRAM) chip, a static-random-access-memory (SRAM) chip, a logic chip, an analog chip, a power device, a regulator, a power management device, a global-positioning-system (GPS) chip, a Bluetooth chip, or a system-on chip (SOC) comprising a central-processing-unit (CPU) circuit block, a graphics-processing-unit (GPU) circuit block, a baseband circuit block, a digital-signal-processing (DSP) circuit block, a memory circuit block, a Bluetooth circuit block, a global-positioning-system (GPS) circuit block, a wireless local area network (WLAN) circuit block and a modem circuit block.

3. The system-in package of claim 1 further comprising a substrate under the first polymer layer, wherein the first chip and the second chip are over the substrate, wherein the substrate comprises a mother board, a printed circuit board, a ball-grid-array (BGA) substrate, a metal substrate, a glass substrate, or a ceramic substrate.

4. The system-in package of claim 1 further comprising a third metal layer over the top surface of the first polymer layer, wherein the third metal layer and the first metal layer are at a same horizontal level, wherein the second chip is further vertically over the third metal layer, wherein the third metal layer provides a power interconnect, a ground interconnect or a signal interconnect.

5. The system-in package of claim 1 further comprising a thermal spreading plane over the first chip, over the second chip, over the second polymer layer, over the second metal bump and over the second metal layer, wherein the first chip and the second chip are connected to the thermal spreading plane.

6. The system-in package of claim 1, wherein the first metal bump comprises a first copper layer having a thickness between 5 and 50 micrometers, wherein the second metal bump comprises a second copper layer having a thickness between 15 and 520 micrometers.

7. The system-in package of claim 1, wherein the first chip comprises a third metal bump in the first polymer layer, wherein a top surface of the third metal bump is not covered by the first polymer layer, wherein the first metal layer is further on the top surface of the third metal bump, wherein the first metal bump is connected to the third metal bump through, in sequence, the second metal layer, the second metal bump and the first metal layer.

8. The system-in package of claim 1, wherein the first metal layer provides a power interconnect, a ground interconnect or a signal interconnect.

9. The system-in package of claim 1 further comprising a third metal layer over the top surface of the first polymer layer and over the first chip, a third chip in the second polymer layer, a third metal bump in the second polymer layer and over the third metal layer, and a fourth metal layer on a top surface of a fourth metal bump of the third chip, on a top surface of the third metal bump and over the top surface of the second polymer layer, wherein the fourth metal bump is in the second polymer layer, wherein the top surface of the third metal bump and the top surface of the fourth metal bump are not covered by the second polymer layer, wherein the fourth metal layer connects the third metal bump to the fourth metal bump, wherein the third metal bump is higher than the fourth metal bump, wherein the fourth metal bump is connected to the first chip through, in sequence, the fourth metal layer, the third metal bump and the third metal layer.

10. The system-in package of claim 1, wherein the total number of bit lines in parallel data communication between the first and second chips is more than 128, and one of the bit lines is provided by the first and second metal layers and the first and second metal bumps.

11. A system-in package comprising:

a substrate;

a first polymer layer over the substrate;

a first chip in the first polymer layer and over the substrate, wherein the first chip comprises a first metal bump and a second metal bump;

a third metal bump in the first polymer layer and over the substrate, wherein the third metal bump is connected to a pad of the substrate, wherein the third metal bump is higher than the first metal bump and higher than the second metal bump, wherein a top surface of the first metal bump, a top surface of the second metal bump and a top surface of the third metal bump are not covered by the first polymer layer;

a first metal layer on the top surface of the first metal bump, on the top surface of the third metal bump and over a top surface of the first polymer layer, wherein the first metal layer connects the first metal bump to the third metal bump, wherein the first metal bump is connected to the pad of the substrate through, in sequence, the first metal layer and the third metal bump;

a second metal layer on the top surface of the second metal bump and over the top surface of the first polymer layer, wherein the second metal layer is connected to the second metal bump;

a second polymer layer over the first polymer layer, over the first metal layer, over the second metal layer and over the first chip;

a second chip in the second polymer layer, wherein the second chip comprises a fourth metal bump;

a fifth metal bump in the second polymer layer, wherein the fifth metal bump is connected to the second metal layer, wherein the fifth metal bump is higher than the fourth metal bump, wherein a top surface of the fourth metal bump and a top surface of the fifth metal bump are not covered by the second polymer layer; and

a third metal layer on the top surface of the fourth metal bump, on the top surface of the fifth metal bump and over a top surface of the second polymer layer, wherein the third metal layer connects the fourth metal bump to the fifth metal bump, wherein the fourth metal bump is connected to the second metal bump through, in sequence, the third metal layer, the fifth metal bump and the second metal layer.

12. The system-in package of claim 11, wherein the substrate comprises a mother board, a printed circuit board, a ball-grid-array (BGA) substrate, a metal substrate, a glass substrate or a ceramic substrate.

13. The system-in package of claim 11, wherein the first chip comprises a central-processing-unit (CPU) chip, a baseband chip, a graphics-processing-unit (GPU) chip, a digital-signal-processing (DSP) chip, a wireless local area network (WLAN) chip, a memory chip, a flash memory chip, a dynamic-random-access-memory (DRAM) chip, a static-random-access-memory (SRAM) chip, a logic chip, an analog chip, a power device, a regulator, a power management device, a global-positioning-system (GPS) chip, a Bluetooth chip, or a system-on chip (SOC) comprising a central-processing-unit (CPU) circuit block, a graphics-processing-unit (GPU) circuit block, a baseband circuit block, a digital-signal-processing (DSP) circuit block, a memory circuit block, a Bluetooth circuit block, a global-positioning-system (GPS) circuit block, a wireless local area network (WLAN) circuit block and a modem circuit block.

14. The system-in package of claim 11 further comprising a fourth metal layer over the top surface of the first polymer layer, wherein the second chip is further vertically over the fourth metal layer, wherein the fourth metal layer provides a power interconnect, a ground interconnect or a signal interconnect.

15. The system-in package of claim 11 further comprising a thermal spreading plane over the first chip, over the second chip, over the second polymer layer, over the fifth metal bump and over the third metal layer, wherein the first chip and the second chip are connected to the thermal spreading plane.

16. The system-in package of claim 11, wherein the fourth metal bump comprises a first copper layer having a thickness between 5 and 50 micrometers, wherein the fifth metal bump comprises a second copper layer having a thickness between 15 and 520 micrometers.

17. The system-in package of claim 11, wherein the second metal layer comprises a first copper layer having a thickness between 2 and 30 micrometers, wherein the third metal layer comprises a second copper layer having a thickness between 2 and 30 micrometers.

18. The system-in package of claim 11, wherein the third metal layer provides a power interconnect, a ground interconnect or a signal interconnect.

19. The system-in package of claim 11 further comprising a passive component in or over the second polymer layer.

20. The system-in package of claim 11, wherein the second chip is further vertically over the second metal layer.