ENCODERS, DECODERS, CODECS AND SYSTEMS AND PROCESSES FOR THEIR OPERATION AND MANUFACTURE

• US 20100290533A1
• Filed: 05/10/2010
• Published: 11/18/2010
• Est. Priority Date: 05/15/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Minagawa, Yusuke
• Granted Patent: US 9,391,635 B2
• Time in Patent Office: Days
• US Class Current: 375/240.23
• CPC Class Codes: H03M 7/40 Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
• CPC Class Codes: H03M 7/46 Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A block encode circuit (800) including a scanner (820) operable to scan a block having data values spaced apart in the block by run-lengths to produce a succession of pairs of values of Level and Run representing each data value and run-length, and wherein the Level values include one or more AC values succeeded by a DC value in the succession, and a Run-Level encoder (830) responsive to said scanner (820) to encode the values of Level and Run in a same AC to DC order as in the succession of pairs of values from said scanner (820) to deliver an encoded output. Other encoders, decoders, codecs and systems and processes for their operation and manufacture are disclosed.

Claims

1. A block encode circuit comprising:

a scanner operable to scan a block having data values spaced apart in the block by run-lengths to produce a succession of pairs of values of Level and Run representing each data value and run-length, and wherein the Level values include one or more AC values succeeded by a DC value in the succession; and

a Run-Level encoder responsive to said scanner to encode the values of Level and Run in a same AC to DC order as in the succession of pairs of values from said scanner to deliver an encoded output.

2. The block encode circuit claimed in claim 1 for use with information from multiple coding tables, said Run-Level encoder including a memory space for only a single such coding table, and further including a symbol encoder to encode the succession of pairs of values, said symbol encoder coupled to directly access only said memory space to obtain coding table information, whereby coding table memory space is reduced.

3. The block encode circuit claimed in claim 2 further comprising a store for a plurality of different coding tables, and a selection circuit operable to supply a selection signal to said store to deliver a single applicable coding table at a time to said memory space.

4. The block encode circuit claimed in claim 3 wherein said store is a re-usable store selected from the group consisting of 1) cache, and 2) random access memory (RAM), whereby the memory space for the single coding table saves overall space for the block encode circuit.

5. The block encode circuit claimed in claim 1 further comprising a selection circuit responsive at least one such value from said scanner to select information to feed into said Run-Level encoder.

6. The block encode circuit claimed in claim 5 wherein said selection circuit is fed unbuffered from said scanner, whereby operations of said Run-Level encoder are at least partially parallelized with said scanner.

7. The block encode circuit claimed in claim 1 further comprising a buffer for holding the block, said scanner including a read counter to read the buffer in an AC to DC order to deliver each read datum, said scanner having a level register and further including a level detector to register a read datum that is a Level value to said level register, and said scanner further including a run counter responsive to said level detector to then count up a Run value until said level detector encounters a next Level value, said level detector coupled to actuate said Run-Level encoder.

8. The block encode circuit claimed in claim 7 wherein said level detector is responsive to the DC coefficient to hold said run counter inactive and to assert a DC encode enable to said Run-Level encoder.

9. The block encode circuit claimed in claim 1 further comprising a subtraction circuit, a frame buffer coupled to feed an image frame to an input of said subtraction circuit, an image prediction circuit coupled to another input of said subtraction circuit, and an image transform-based circuit fed by said subtraction circuit to produce the block of data values.

10. A manufacturing process comprising fabricating on a single integrated circuit chip a block buffer and a scanner operable to scan the block buffer for data values spaced apart in the block by run-lengths to produce a succession of pairs of values of Level and Run representing each data value and run-length, and wherein the Level values include one or more AC values succeeded by a DC value in the succession, and a Run-Level encoder responsive to said scanner to code the values of Level and Run in a same AC to DC order to deliver an encoded output.

11. An image encoder process comprising electronically scanning image transform-based coefficients in a particular scanning order and variable-length coding the image transform-based coefficients in substantially the same order.

12. The encoder process claimed in claim 11 wherein the coefficients are in a block, and the scanning and variable-length coding are pipelined for concurrent execution with a latency of less than one block.

13. The encoder process claimed in claim 11 wherein the scanning order of the coefficients is from AC to DC.

14. The encoder process claimed in claim 11 wherein the scanning produces Run and Level data and the variable-length coding consumes the Run and Level data in the same order as the scanning produces that Run and Level data.

15. The encoder process claimed in claim 14 wherein the variable-length coding consumes the Run and Level data from the scanning unbuffered, whereby block-level pipeline latency is eliminated.

16. The encoder process claimed in claim 11 wherein the scanning includes starting scanning of the coefficients from a highest AC coefficient downward, and when a Level coefficient is encountered then temporarily storing the Level coefficient and counting a Run until a next Level coefficient is encountered in the scanning order, the variable-length encoding using the temporarily stored Level coefficient and the Run thus counted.

17. The encoder process claimed in claim 11 wherein the scanning order of the coefficients is from AC to DC and when the scanning reaches a DC coefficient, then the variable-length encoding encodes the DC coefficient with no Run length.

18. A reduced-memory encoder comprising:

an encoder operable to encode a series of data input thereto, the encode dependent on coding information in a plurality of different coding tables;

a re-usable store space for the plurality of different coding tables for encoder support, the same store space otherwise re-usable for other uses than encoder support;

a coding memory space able only to hold substantially fewer than the plurality of coding tables, said encoder coupled to access only said coding memory space instead of said re-usable store space for coding table information; and

a selection circuit operable to supply a selection signal to said store to deliver an applicable coding table to said coding memory space.

19. The reduced-memory encoder claimed in claim 18 wherein said re-usable store space is selected from the group consisting of 1) cache, and 2) random access memory (RAM), said coding memory space having capacity for only a single coding table whereby saving space for said encoder.

20. The reduced-memory encoder claimed in claim 18 wherein said selection circuit is responsive unbuffered to at least some data from the same series of data input to said encoder so that the delivery of the applicable coding table to said coding memory space is hidden.

21. The reduced-memory encoder claimed in claim 18 wherein said encoder includes an entropy encoder, and further includes a symbol encoder coupled to access only said coding memory space for such coding table information and said symbol encoder operable to encode the series of data input thereto to supply symbols to said entropy encoder.

22. The reduced-memory encoder claimed in claim 21 wherein said selection circuit is operable to also supply a selection control to said entropy encoder.

23. The reduced-memory encoder claimed in claim 18, wherein the series of data includes level data and run data, and further comprising a run counter for supplying a run datum subsequent to a corresponding level datum, said selection circuit responsive to the level datum so that the delivery of the applicable coding table to said coding memory space is hidden behind operation of said run counter.

24. A manufacturing process comprising fabricating on a single integrated circuit chip a code-related processing circuit dependent on coding information in a plurality of different coding tables to encode a series of data input thereto, a cache memory having a capacity sufficient to hold the different coding tables, a coding memory space substantially smaller than said cache memory, said code-related processing circuit coupled to access only said coding memory space instead of said cache memory for such coding information, and a selection circuit operable to supply a selection signal to said cache memory to deliver an applicable coding table to said coding memory space.

25. A decode circuit comprising:

a Run-Level decoder operable to deliver a succession of pairs of values, each pair including a Run value and a Level value; and

an inverse scanner responsive to the succession of pairs of values to populate a block with the Level values including one or more AC values and a DC value, the Level values spaced apart in the block by runs having lengths represented by the Run values, and said inverse-scanner is operable to sequentially populate the block using the Level values and the Run values in a same AC to DC order as in the succession of pairs of values from said Run-Level decoder.

26. The decode circuit claimed in claim 25 for use with coding table information, said Run-Level decoder including a memory space for only a single coding table and further including a symbol decoder to supply the succession of pairs of values, said symbol decoder coupled to directly access only said memory space for the coding table information, whereby coding table memory space is reduced.

27. The decode circuit claimed in claim 26 further comprising a store for a plurality of different coding tables, and a selection circuit operable to supply a selection signal to said store to deliver a single applicable coding table at a time to said memory space.

28. The decode circuit claimed in claim 27 wherein said store is a re-usable store selected from the group consisting of 1) cache, and 2) random access memory (RAM), whereby the memory space for the single coding table saves overall space for the decode circuit.

29. The decode circuit claimed in claim 25 further comprising a selection circuit responsive to the Run-Level decoder to select information to feed into said Run-Level decoder.

30. A decoding process comprising:

variable-length decoding according to a decoding order to supply image transform-based coefficients and Run values; and

inverse-scanning the coefficients using the Run values into a block in substantially the same order as the decoding order.

31. The decoding process claimed in claim 30 wherein the inverse-scanning writes each successive coefficient at a position in the block, the position determined from a previous such position and a Run value.

32. The decoding process claimed in claim 31 wherein the variable-length decoding and the inverse-scanning are pipelined for concurrent execution with a latency of less than one block.

33. The decoding process claimed in claim 30 further comprising inverse-transforming the block to produce inverse-transformed data and summing an image prediction with the inverse-transformed data, whereby a decoded image is obtainable.

34. A reduced-memory decoder comprising:

a decoder operable to decode a series of data input thereto, the decode dependent on coding information in a plurality of different coding tables;

a re-usable store space for the plurality of different coding tables for decoder support, the same store space otherwise re-usable for other uses than decoder support;

a decoding memory space able only to hold substantially fewer than the plurality of coding tables, said decoder coupled to access only said decoding memory space instead of said re-usable store space for coding table information; and

a selection circuit operable to supply a selection signal to said store to deliver an applicable coding table to said decoding memory space.

35. The reduced-memory decoder claimed in claim 34 wherein said re-usable store space is selected from the group consisting of 1) cache, and 2) random access memory (RAM), and said decoding memory space is able only to hold a single coding table, whereby saving space for said decoder.

36. The reduced-memory decoder claimed in claim 34 wherein said selection circuit is responsive unbuffered to a succession of data output from said decoder.

37. The reduced-memory decoder claimed in claim 34 further comprising an inverse-scan circuit responsive to data output from said decoder according to operations approximately concurrent with the delivery of the applicable coding table to said coding memory space.

38. An electronic system comprising:

a modem operable to receive a transmission;

a Run-Level decoder responsive to the transmission to deliver a succession of pairs of values, each pair including a Run value and a Level value;

an inverse scanner responsive to the succession of pairs of values to populate a block with the Level values including one or more AC values and a DC value, the Level values spaced apart in the block by runs having lengths represented by the Run values, and said inverse-scanner operable to sequentially populate the block using the Level values and the Run values in a same order as in the succession of pairs of values from said Run-Level decoder; and

a display circuit operable in response to said inverse scanner to form an image signal.

39. The electronic system claimed in claim 38 further adapted to form a device selected from the group consisting of 1) cellular telephone, 2) projector, 3) mobile entertainment device, 4) personal computer.