Power Managed Lock Optimization

• US 20100293401A1
• Filed: 05/13/2009
• Published: 11/18/2010
• Est. Priority Date: 05/13/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Kumar, Puneet, Semeria, Bernard J., Smith, Michael J., Wadhawan, Ruchi, de Cesare, Josh P.
• Granted Patent: US 8,156,275 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

Claims

1. An apparatus comprising:

a timer unit configured to pulse a signal at each expiration of a selected time interval; and

a processor coupled to receive the signal from the timer unit, wherein the processor is configured to execute a first instruction that is defined in an instruction set architecture implemented by the processor, wherein the first instruction is defined to cause the processor to enter a low power state for a thread that includes the first instruction, and wherein the processor is configured to exit the low power state for the thread responsive to the pulse on the signal from the timer unit and to continue execution with an instruction following the first instruction.

2. The apparatus as recited in claim 1 further comprising a second processor that implements the instruction set architecture, wherein the second processor is also coupled to receive the signal from the timer unit and is configured to exit the low power state for the thread responsive to the pulse on the signal.

3. The apparatus as recited in claim 1 further comprising a second processor that implements the instruction set architecture and a second timer unit configured to pulse a second signal at each expiration of the selected time interval, wherein the second processor is coupled to receive the second signal from the second timer unit and is configured to exit the low power state for the thread responsive to the pulse on the second signal.

4. The apparatus as recited in claim 1 wherein the processor is further configured to exit the low power state responsive to receiving a send event message from another processor.

5. The apparatus as recited in claim 1 wherein the selected time interval is programmable in the timer unit.

6. The apparatus as recited in claim 1 wherein the selected time interval is dependent on a typical expected time that a thread holds the lock.

7. A computer accessible medium storing a plurality of instructions which, when executed by a processor:

attempt to acquire a lock;

responsive to failing to acquire the lock, determine whether or not an additional iteration is permitted; and

responsive to determining that the additional iteration is permitted, wait for an event prior to initiating another iteration, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption while the plurality of instructions is attempting to acquire the lock.

8. The computer accessible medium as recited in claim 7 wherein the plurality of instructions, when executed responsive to an exit from the low power state:

attempt to acquire the lock;

responsive to acquiring the lock, perform one or more operations that required the lock; and

release the lock.

9. The computer accessible medium as recited in claim 8 wherein releasing the lock comprises transmitting a send event message that causes the exit from the low power state in a processor receiving the send event message.

10. The computer accessible medium as recited in claim 7 wherein the plurality of instructions, when executed responsive to an exit from the low power state:

attempt to acquire the lock;

responsive to failing to acquire the lock, determine whether or not another additional iteration is permitted; and

responsive to determining that another additional iteration is not permitted, block the thread.

11. The computer accessible medium as recited in claim 7 wherein determining whether or not the additional iteration is permitted comprises updating an iteration count and testing the count for expiration.

12. The computer accessible medium as recited in claim 7 wherein determining whether or not the additional iteration is permitted comprises reading a time service provided by an operating system under execution by the processor and determining an amount of time elapsing while attempting to acquire the lock.

13. A computer accessible medium storing a plurality of instructions which, when executed by a processor:

initialize a timer during initialization of a system including the processor, the timer initialized to a selected amount of time, wherein the timer is configured to assert a signal responsive to each expiration of the selected amount of time, and wherein the processor is configured to exit a low power state responsive to the asserted signal;

iteratively attempt to acquire a lock and wait for an event responsive to failing to acquire the lock, wherein waiting for the event comprises entering the low power state.

14. The computer accessible medium as recited in claim 13 wherein the selected amount of time is dependent on a typical amount of time that a thread holds the lock.

15. The computer accessible medium as recited in claim 14 wherein the plurality of instructions, when executed:

determine that an additional iteration is not permitted, wherein a number of permitted iterations, multiplied by the selected amount of time, is approximately the typical amount of time; and

responsive to determining that the additional iteration is not permitted, block the thread including the plurality of instructions.

16. A method comprising executing instructions by a processor that:

iteratively attempt to acquire a lock and, responsive to failing to acquire the lock, wait for an event;

responsive to a number of iterations expiring, deschedule the thread; and

block rescheduling of the thread until at least a release of the lock occurs.

17. The method as recited in claim 16 further comprising executing instructions by a processor that:

detect the release of the lock;

reschedule the thread; and

attempt to acquire the lock.

18. A processor comprising:

an execution core configured to execute instructions defined in an instruction set architecture implemented by the processor, the instructions including a wait for event instruction, wherein the execution core is configured to enter a low power state responsive to executing the wait for event instruction; and

an event control unit coupled to the execution core and configured to cause the execution core to exit the low power state responsive to an expiration of a predetermined time interval.

19. The processor as recited in claim 18 further comprising a timer unit that is programmed to the predetermined time interval, wherein the event control unit is coupled to the timer unit and is configured to detect the expiration of the predetermined time interval responsive to the timer unit.

20. The processor as recited in claim 18 having a signal input from an external timer unit, wherein the event control unit is coupled to receive the signal and to detect the expiration of the predetermined time interval responsive to the signal.