System for Error Control Coding for Memories of Different Types and Associated Methods

• US 20100293436A1
• Filed: 01/31/2008
• Published: 11/18/2010
• Est. Priority Date: 01/31/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lastras-Montano, Luis A., Coteus, Paul W., Trager, Barry M., Maule, Warren Edward, Winograd, Shmuel
• Granted Patent: US 8,185,800 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/154 Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial
• CPC Class Codes: H03M 13/1545 Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
• CPC Class Codes: H03M 13/353 Adaptation to the channel
• CPC Class Codes: H03M 13/3707 Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
• CPC Class Codes: H03M 13/6511 Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields

Abstract

A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.

Claims

1. A system for error control coding for memories of different types, wherein the type of a memory is determined by the type of the chips used in the memory, the system comprising:

error control encoder circuitry to substantially encode data for storage in memories of different types; and

error control decoder circuitry to substantially decode encoded data received from memories of different types;

wherein the error control circuitry has a fast decoding mode and a slow decoding mode.

2. The system of claim 1 wherein the type of the memory is passed to said error control decoder circuitry.

3. The system of claim 1 wherein the same error control encoder circuitry is used independently of the type of the memory.

4. The system of claim 1 wherein the type of the chips is determined by an input pin count and an output pin count for each of said chips.

5. The system of claim 4 wherein said chips have an input pin count and an output pin count of 4, 8, or 16.

6. The system of claim 1 wherein said error control decoder circuitry'"'"'s error handling capabilities can vary as the type of the memory varies.

7. The system of claim 1 wherein the slow decoding mode is affected by the type of memory from which data is being received.

8. The system of claim 1 wherein said error control decoder circuitry supports different numbers of memory chip failures for memories of different types.

9. A method for error control coding for memories of different types, wherein the type of a memory is determined by the type of the chips used in the memory, the method comprising:

using error control encoder circuitry to substantially encode data for storage in memories of different types; and

using error control decoder circuitry to substantially decode encoded data received from memories of different types;

wherein the error control circuitry has a fast decoding mode and a slow decoding mode.

10. The method of claim 9 wherein the type of the memory is passed to the error control decoder circuitry.

11. The method of claim 9 wherein the same error control encoder circuitry is used independently of the type of the memory.

12. The method of claim 9 wherein the type of the memory chips is determined by an input pin count and an output pin count for each of the memory chips.

13. The method of claim 9 wherein the error control decoder circuitry'"'"'s error handling capabilities can vary as the type of the memory varies.

14. The method of claim 9 wherein the error control encoder circuitry uses a parity check matrix based upon a Reed-Solomon code.

15. The method of claim 9 wherein the error control decoder circuitry supports different numbers of memory chip failures for memories of different types.

16. A computer program product embodied in a tangible media comprising:

computer readable program codes coupled to the tangible media for error control coding for memories of different types, wherein the type of a memory is determined by the type of the chips used in the memory, the computer readable program codes configured to cause the program to;

use error control encoder algorithms to substantially encode data for storage in memories of different types; and

use error control decoder algorithms to substantially decode encoded data received from memories of different types;

wherein the error control circuitry has a fast decoding mode and a slow decoding mode.

17. The computer program product of claim 16 wherein the type of the memory is passed to the error control decoder algorithms.

18. The computer program product of claim 16 further comprising program code configured to:

use the same error control encoder algorithms independently of the type of the memory.

19. The computer program product of claim 16 further comprising program code configured to:

allow for the error control decoder algorithm'"'"'s error handling capabilities to vary as the memory type varies.

20. The computer program product of claim 16 further comprising program code configured to:

support different numbers of memory chip failures for memories of different types in the error control decoder algorithms.