Nanocrystal Based Universal Memory Cells, and Memory Cells

• US 20100295118A1
• Filed: 06/14/2010
• Published: 11/25/2010
• Est. Priority Date: 10/15/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 8,193,568 B2
• Time in Patent Office: Days
• US Class Current: 257/325
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: Y10S 977/777 Metallic powder or flake
• CPC Class Codes: Y10S 977/943 Information storage or retrieval using nanostructure

Abstract

Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.

Claims

1-35. -35. (canceled)

36. A memory cell comprising:

a first charge-trapping plane, the first charge-trapping plane comprising two different types of nanoparticles that differ in work function relative to one another, the two types of nanoparticles of the first charge-trapping plane being about the same in average maximum cross-sectional dimension as one another and being a first type of nanoparticles and a second type of nanoparticles;

a second charge-trapping plane over the first charge-trapping plane, the second charge-trapping plane comprising a third type of nanoparticles that have a third average maximum cross-sectional dimension; and

a third charge-trapping plane over the second charge-trapping plane, the third charge-trapping plane comprising a fourth type of nanoparticles that have a fourth average maximum cross-sectional dimension, the fourth average maximum cross-sectional dimension being at least about 10% greater than the third average maximum cross-sectional dimension.

37. The memory cell of claim 36 wherein one of the first and second types of nanoparticles comprises tungsten and the other comprises platinum.

38. The memory cell of claim 36 wherein the third and fourth types of nanoparticles comprise the same composition as one another.

39. The memory cell of claim 36 wherein the third and fourth types of nanoparticles comprise different compositions from one another.

40. The memory cell of claim 36 wherein one of the third and fourth types of nanoparticles comprises tungsten and the other comprises platinum.

41. The memory cell of claim 36 wherein the third type of nanoparticles comprises tungsten and the fourth type of nanoparticles comprises platinum.

42. The memory cell of claim 36 wherein the third average maximum cross-sectional dimension of the third type of nanoparticles is greater than the average maximum cross-sectional dimension of the two types of nanoparticles of the first charge-trapping plane.

43. A memory cell comprising:

a first charge-trapping plane, the first charge-trapping plane comprising two different types of nanoparticles that differ in work function relative to one another, the two types of nanoparticles of the first charge-trapping plane being about the same in average maximum cross-sectional dimension as one another and being a first type of nanoparticles and a second type of nanoparticles;

a first dielectric over and between the nanoparticles of the first charge-trapping plane;

a second charge-trapping plane over the first dielectric, the second charge-trapping plane comprising a third type of nanoparticles that have a third average maximum cross-sectional dimension;

a second dielectric over and between the third type of nanoparticles;

a third charge-trapping plane over the second dielectric, the third charge-trapping plane comprising a fourth type of nanoparticles that have a fourth average maximum cross-sectional dimension, the fourth average maximum cross-sectional dimension being at least about 10% greater than the third average maximum cross-sectional dimension;

a third dielectric over and between the fourth type of nanoparticles; and

a control gate over the third dielectric.

44. The memory cell of claim 43 wherein one of the first and second types of nanoparticles comprises tungsten and the other comprises platinum.

45. The memory cell of claim 43 wherein the third and fourth types of nanoparticles comprise the same composition as one another.

46. The memory cell of claim 43 wherein the third and fourth types of nanoparticles comprise different compositions from one another.

47. The memory cell of claim 43 wherein one of the third and fourth types of nanoparticles comprises tungsten and the other comprises platinum.

48. The memory cell of claim 43 wherein the third type of nanoparticles comprises tungsten and the fourth type of nanoparticles comprises platinum.

49. The memory cell of claim 43 wherein:

the first dielectric comprises silicon dioxide;

the second dielectric comprises one or both of hafnium silicon oxynitride and zirconium silicon oxynitride; and

the third dielectric comprises one or both of hafnium silicon oxynitride and zirconium silicon oxynitride.

50. A memory cell comprising:

a tunnel dielectric comprising one or both hafnium oxide or zirconium oxide, the tunnel dielectric being over a monocrystalline silicon base;

a first charge-trapping plane over the tunnel dielectric, the first charge-trapping plane comprising two different types of nanoparticles that differ in work function relative to one another, the two types of nanoparticles of the first charge-trapping plane being about the same in average maximum cross-sectional dimension as one another and being a first type of nanoparticles and a second type of nanoparticles;

a first dielectric over and between the nanoparticles of the first charge-trapping plane, the first dielectric layer having a first equivalent oxide thickness over the first charge-trapping plane;

a second charge-trapping plane over the first dielectric, the second charge-trapping plane comprising a third type of nanoparticles that have a third average maximum cross-sectional dimension;

a second dielectric over and between the third type of nanoparticles, the second dielectric having a second equivalent oxide thickness over the second charge-trapping plane;

the second equivalent oxide thickness being at least about 10% greater than the first equivalent oxide thickness;

a third charge-trapping plane over the second dielectric, the third charge-trapping plane comprising a fourth type of nanoparticles that have a fourth average maximum cross-sectional dimension, the fourth average maximum cross-sectional dimension being at least about 10% greater than the third average maximum cross-sectional dimension;

a third dielectric over and between the fourth type of nanoparticles; and

a control gate over the third dielectric.