METHODS AND SYSTEMS FOR FABRICATION OF MEMS CMOS DEVICES
First Claim
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1. A method for manufacturing a chip comprising a MEMS arranged in an integrated circuit comprising:
- producing layers, in one or more stages, that form electrical and/or electronic elements on a semiconductor material substrate,producing a structure of interconnection layers, during an interconnection stage, comprising depositing at least one bottom layer of conductor material and one top layer of conductor material, separated by at least one layer of dielectric material, the at least one bottom layer of conductor material including a bottom layer of conductor material formed above and in contact with an Inter Level Dielectric (ILD) layer, andforming at least one hollow space of the MEMS in the structure of interconnection layers using gaseous HF during an attack stage, the MEMS being formed above the bottom layer of conductor material in contact with the ILD layer.
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Abstract
A MEMS integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material. The bottom layer may be formed above and in contact with an Inter Dielectric Layer. The circuit also includes a hollow space within the structure of interconnection layers and a MEMS device in communication with the structure of interconnection layers.
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Citations
32 Claims
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1. A method for manufacturing a chip comprising a MEMS arranged in an integrated circuit comprising:
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producing layers, in one or more stages, that form electrical and/or electronic elements on a semiconductor material substrate, producing a structure of interconnection layers, during an interconnection stage, comprising depositing at least one bottom layer of conductor material and one top layer of conductor material, separated by at least one layer of dielectric material, the at least one bottom layer of conductor material including a bottom layer of conductor material formed above and in contact with an Inter Level Dielectric (ILD) layer, and forming at least one hollow space of the MEMS in the structure of interconnection layers using gaseous HF during an attack stage, the MEMS being formed above the bottom layer of conductor material in contact with the ILD layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A chip comprising an integrated circuit, said integrated circuit comprising:
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one or more layers forming electrical and/or electronic elements on a substrate of semiconductor material, a structure of interconnection layers comprising at least one bottom layer of conductor material and one top layer of conductor material, separated by at least one layer of dielectric material, the at least one bottom layer of conductor material including a bottom layer of conductor material formed above and in contact with an ILD layer, and at least one MEMS arranged in the structure of interconnection layers, wherein the MEMS comprises at least one hollow space, and a portion of the hollow space is arranged over the bottom layer of conductor material in contact with the ILD layer.
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18. A method for manufacturing a MEMS integrated circuit comprising:
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producing layers, in one or more stages, that form electrical and/or electronic elements on a semiconductor material substrate, producing a structure of interconnection layers, during an interconnection stage, comprising depositing at least one bottom layer of conductor material and one top layer of conductor material, separated by at least one layer of dielectric material, the at least one bottom layer of conductor material including a bottom layer of conductor material formed above and in contact with an Inter Level Dielectric (ILD) layer, producing a vias extending continuously across at least two layers of the plurality of layers, using gaseous HF to form a hollow space in the structure of interconnection layers, and forming at least a portion of a MEMS device within the structure of interconnection layers. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A MEMS integrated circuit comprising:
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a plurality of layers, a portion of which includes one or more electronic elements on a semiconductor material substrate, a structure of interconnection layers including a bottom layer of conductor material and a top layer of conductor material, separated by at least one layer of dielectric material, the bottom layer of conductor being formed above and in contact with an ILD layer, at least one vias extending continuously across at least two layers of the plurality of layers, a hollow space in the structure of interconnection layers, and a MEMS device in communication with the structure of interconnection layers.
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Specification