METHODS AND SYSTEMS FOR FABRICATION OF MEMS CMOS DEVICES

• US 20100295138A1
• Filed: 05/20/2010
• Published: 11/25/2010
• Est. Priority Date: 05/20/2009
• Status: Abandoned Application

• Current Assignee: Baolab Microsystems SL
• Original Assignee: Baolab Microsystems SL
• Inventors: Valle Fraga, Juan Jose, Llamas Morote, Marco Antonio, Sabir, Tayyib, Montanya Silvestre, Josep
• Application Number:
  US12/784,024
• Publication Number:
  US 20100295138A1
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/351 Thermal stress

Abstract

A MEMS integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material. The bottom layer may be formed above and in contact with an Inter Dielectric Layer. The circuit also includes a hollow space within the structure of interconnection layers and a MEMS device in communication with the structure of interconnection layers.

Claims

1. A method for manufacturing a chip comprising a MEMS arranged in an integrated circuit comprising:

producing layers, in one or more stages, that form electrical and/or electronic elements on a semiconductor material substrate,

producing a structure of interconnection layers, during an interconnection stage, comprising depositing at least one bottom layer of conductor material and one top layer of conductor material, separated by at least one layer of dielectric material, the at least one bottom layer of conductor material including a bottom layer of conductor material formed above and in contact with an Inter Level Dielectric (ILD) layer, and

forming at least one hollow space of the MEMS in the structure of interconnection layers using gaseous HF during an attack stage, the MEMS being formed above the bottom layer of conductor material in contact with the ILD layer.

2. The method according to claim 1, wherein the top layer of conductor material comprises a plurality of holes sized to allow the gaseous HF pass through and inhibit nitrides from passing through.

3. The method according to claim 2 comprising forming the plurality of holes such that a portion is aligned above the MEMS.

4. The method according to claim 2, wherein a hole in the plurality of holes has a diameter less than or equal to 100 nm, 200 nm, 300 nm, 400 nm, or 500 nm.

5. The method according to claim 2, wherein additional stages are carried out between the interconnection stage and the attack stage, the additional stages comprising:

forming a passivation layer during a production stage, wherein the passivation layer comprising a bottom layer of silicon dioxide and a top layer of silicon nitride arranged on top of the top layer of conductor material, and

removing, at least partially, the passivation layer during a removal stage.

6. The method according to claim 5, comprising forming an ALD coating during an ALD coating stage after the attack stage.

7. The method according to claim 6, wherein the MEMS comprises a mobile element that is moved during the ALD coating stage.

8. The method according to any of the claim 5, further comprising a stage of producing a sealing layer.

9. The method according to claim 8, wherein the top layer of conductor material undergoes an ALD coating before the stage of producing the sealing layer.

10. The method according to claim 5, wherein the stage of at least partially removing the passivation layer produces openings that are arranged over plates of conductor material belonging to the top layer of conductor material, and comprising a stage of producing a sealing layer to fill, at least partially, the hollow space between each of the openings and the corresponding plate of conductor material.

11. The method according to claim 1 comprising:

establishing at least one direct interconnection between the substrate and at least one of the layers of conductor material by means of an HF resistant material.

12. The method according to claim 11, wherein a layer of amorphous silicon exists between the substrate and the conductor material.

13. The method according to claim 12, wherein the MEMS comprises a conductor element including a movable part.

14. The method according to claim 13, wherein the MEMS comprises at least two capacitor plates arranged to produce electrostatic fields over the movable part that are capable of moving the movable part.

15. The method according to claim 14, wherein the MEMS operates as a relay, the MEMS comprising at least two contact points in an electric circuit arranged to allow the movable part to be in contact simultaneously with both contact points.

16. The method according to claim 1, wherein the MEMS comprises a device including at least one of an electrical relay, accelerometer, inclinometer, Coriolis force detector, pressure sensor, microphone, flow rate sensor, temperature sensor, gas sensor, magnetic field sensor, electro-optical device, optical switching matrix, image projector device, analogue connection matrix, electromagnetic signal emission and/or reception device, power supply, DC/DC converter, AC/DC converter, DC/AC converter, A/D converter, D/A converter, and power amplifier.

17. A chip comprising an integrated circuit, said integrated circuit comprising:

one or more layers forming electrical and/or electronic elements on a substrate of semiconductor material,

a structure of interconnection layers comprising at least one bottom layer of conductor material and one top layer of conductor material, separated by at least one layer of dielectric material, the at least one bottom layer of conductor material including a bottom layer of conductor material formed above and in contact with an ILD layer, and

at least one MEMS arranged in the structure of interconnection layers, wherein the MEMS comprises at least one hollow space, and a portion of the hollow space is arranged over the bottom layer of conductor material in contact with the ILD layer.

18. A method for manufacturing a MEMS integrated circuit comprising:

producing layers, in one or more stages, that form electrical and/or electronic elements on a semiconductor material substrate,

producing a structure of interconnection layers, during an interconnection stage, comprising depositing at least one bottom layer of conductor material and one top layer of conductor material, separated by at least one layer of dielectric material, the at least one bottom layer of conductor material including a bottom layer of conductor material formed above and in contact with an Inter Level Dielectric (ILD) layer,

producing a vias extending continuously across at least two layers of the plurality of layers,

using gaseous HF to form a hollow space in the structure of interconnection layers, and

forming at least a portion of a MEMS device within the structure of interconnection layers.

19. The method of claim 18 comprising stacking the plurality of layers together to form an equivalent thicker metal layer joined by a plurality of vias.

20. The method of claim 18 comprising attaching the MEMS device to the structure of the interconnection layers via a soft spring comprised of one or more metal layers joined by a plurality of vias.

21. The method of claim 18 comprising forming the MEMS device which comprises a part that is detached from the MEMS structure and is mechanically free.

22. The method of claim 18 comprising adding a partition of HF resistant material around the MEMS device, wherein the partition of HF resistant material comprises the continuous vias.

23. The method of claim 18 wherein the MEMS device comprises a multi-level memory programmable by changing the resistance value of a via in a cell of the memory by overpassing the electromigration limit for a limited period of time.

24. The method of claim 18 comprising producing a passivation layer in the structure of interconnection layers.

25. The method of claim 24 further comprising performing chemical-mechanical polishing on the passivation layer.

26. The method of claim 18 comprising:

manufacturing the MEMS integrated circuit on a wafer, and

performing passivation on a plurality of scribe lines of the wafer.

27. The method of claim 18 comprising producing the at least one layer of dielectric material which comprises a double oxide.

28. The method of claim 18 comprising producing the at least one layer of dielectric material which comprises a single oxide.

29. The method of claim 18 wherein producing the structure of interconnection layers comprises producing:

a top layer of conductor material having a plurality of holes, arranged over the MEMS device; and

a following layer of conductor material having a plurality of holes that are not aligned with the holes of the top layer of conductor material, arranged under the top layer of conductor material.

30. The method of claim 29 comprising:

depositing a passivation layer on the top layer of conductor material, the passivation layer comprising a bottom layer of silicon dioxide and a top layer of silicon nitride,

releasing vaporized HF to etch away the dielectric material separating the layers of conductor material, and

sputtering Al on the passivation layer.

31. The method of claim 29 comprising:

depositing a film of photoresist material on the passivation layer,

removing a portion of the film to form a photoresist mask on the sputtered Al on the passivation layer,

etching away the sputtered Al material not under the mask from the sputtered Al layer, and

removing the photoresist mask to release an Al plugged area.

32. A MEMS integrated circuit comprising:

a plurality of layers, a portion of which includes one or more electronic elements on a semiconductor material substrate,

a structure of interconnection layers including a bottom layer of conductor material and a top layer of conductor material, separated by at least one layer of dielectric material, the bottom layer of conductor being formed above and in contact with an ILD layer,

at least one vias extending continuously across at least two layers of the plurality of layers,

a hollow space in the structure of interconnection layers, and

a MEMS device in communication with the structure of interconnection layers.