SEMICONDUCTOR DEVICE WITH OXIDE DEFINE DUMMY FEATURE

• US 20100295150A1
• Filed: 02/11/2010
• Published: 11/25/2010
• Est. Priority Date: 05/22/2009
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Lee, Tung-Hsing, Chan, Kuei-Ti
• Application Number:
  US12/703,787
• Publication Number:
  US 20100295150A1
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

A semiconductor device includes a substrate, an inductor wiring pattern on the substrate, and at least one oxide define (OD) dummy feature disposed in the substrate under the inductor wiring pattern.

Claims

1. A semiconductor device comprising:

a substrate;

an inductor wiring pattern on the substrate; and

at least one oxide define (OD) dummy feature disposed in the substrate under the inductor wiring pattern.

2. The semiconductor device according to claim 1 wherein the OD dummy feature is further disposed near an active device around the semiconductor device.

3. The semiconductor device according to claim 1 wherein the OD dummy feature occupies at least 5% of a predetermined area under the inductor wiring pattern.

4. The semiconductor device according to claim 3 wherein the predetermined area is about 100-250,000 μ

m².

5. The semiconductor device according to claim 1 wherein the semiconductor device further comprises a shallow trench isolation (STI) pattern under the inductor wiring pattern.

6. The semiconductor device according to claim 1 wherein no dopant is implanted into the OD dummy feature.

7. The semiconductor device according to claim 1 wherein an N type dopant is implanted into the OD dummy feature.

8. The semiconductor device according to claim 1 wherein a P type dopant is implanted into the OD dummy feature.

9. The semiconductor device according to claim 1 wherein no silicide is formed on the OD dummy feature.

10. The semiconductor device according to claim 1 wherein a dielectric is provided between the substrate and the inductor wiring pattern.

11. The semiconductor device according to claim 1 wherein the OD dummy feature is disposed in the substrate within an inductor forming region, and wherein a peripheral region is proximate to the inductor forming region.

12. The semiconductor device according to claim 11 wherein a width of the peripheral region ranges between 0 and 50 micrometers from an edge of the inductor forming region.

13. A semiconductor device comprising:

a substrate;

an inductor wiring pattern on the substrate;

at least one first oxide define (OD) dummy feature disposed in the substrate within an inductor forming region under the inductor wiring pattern; and

at least one second OD dummy feature disposed in the substrate within a peripheral region that is proximate to the inductor forming region.

14. The semiconductor device according to claim 13 wherein active devices are formed less than 20 micrometers away from the peripheral region.

15. The semiconductor device according to claim 13 wherein the peripheral region is an annular region.

16. The semiconductor device according to claim 13 wherein the first OD dummy feature occupies at least 5% of a predetermined area under the inductor wiring pattern.

17. The semiconductor device according to claim 16 wherein the predetermined area is about 100-250,000 μ

m².

18. The semiconductor device according to claim 13 wherein no dopant is implanted into the first and/or second OD dummy features.

19. The semiconductor device according to claim 13 wherein a width of the peripheral region ranges between 0 and 50 micrometers from an edge of the inductor forming region.

20. A semiconductor device comprising:

a substrate;

an inductor wiring pattern on the substrate within an inductor forming region; and

at least one oxide define (OD) dummy feature disposed in the substrate within a peripheral region that is proximate to the inductor forming region.

21. The semiconductor device according to claim 20 wherein no oxide define dummy feature is formed in the substrate within the inductor forming region.

22. The semiconductor device according to claim 20 wherein the peripheral region is an annular region.

23. The semiconductor device according to claim 20 wherein no dopant is implanted into the OD dummy feature.

24. The semiconductor device according to claim 20 wherein an N type dopant is implanted into the OD dummy feature.

25. The semiconductor device according to claim 20 wherein a P type dopant is implanted into the OD dummy feature.

26. The semiconductor device according to claim 20 wherein a width of the peripheral region ranges between 0 and 50 micrometers from an edge of the inductor forming region.

27. The semiconductor device according to claim 20 wherein active devices are formed less than 20 micrometers away from the peripheral region.