Semiconductor device and method for fabricating the same

• US 20100295187A1
• Filed: 06/16/2010
• Published: 11/25/2010
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Aisin AW Company Limited (Aisin Corp.), Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Aisin AW Company Limited (Aisin Corp.), Fuji Electric Systems Company Limited
• Inventors: Ono, Masaki, Aoki, Kazuo, Yoshihara, Katsuhiko, Tsuruoka, Junji
• Granted Patent: US 8,710,666 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/3754 Coating
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4846 with multiple bonds on the same bonding area
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84214 using a laser
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A semiconductor device which can prevent a deterioration in the electrical properties by preventing sputters generated by laser welding from adhering to a circuit pattern or a semiconductor chip and a method for fabricating such a semiconductor device are provided. A connection conductor is bonded to a copper foil formed over a ceramic by a solder and resin is injected to a level lower than a top of the connection conductor. Laser welding is then performed. After that, resin is injected. This prevents sputters generated by the laser welding from adhering to a circuit pattern or a semiconductor chip. As a result, a deterioration in the electrical properties can be prevented.

Claims

1. A semiconductor device comprising:

a circuit pattern formed over an insulating board;

a semiconductor chip bonded over the circuit pattern;

a connection conductor bonded to at least one of the circuit pattern and the semiconductor chip;

an insulating resin which exposes a welding portion of the connection conductor and which covers the circuit pattern and the semiconductor chip; and

an external terminal which passes a main electric current through a main electrode of the semiconductor chip and which is bonded to the welding portion of the connection conductor by laser welding.

2. The semiconductor device according to claim 1, further comprising an upper-layer insulating resin which covers an exposed portion of the connection conductor and the external terminal over the insulating resin.

3. The semiconductor device according to claim 1, wherein:

the semiconductor chip includes one or more signal electrodes in addition to the main electrode; and

the insulating resin covers at least bonding wires which connect the one or more signal electrodes to signal terminals that draw out the one or more signal electrodes.

4. The semiconductor device according to claim 1, wherein the connection conductor has a bent structure in which there is a space between a side bonded to at least one of the circuit pattern and the semiconductor chip and the welding portion.

5. A semiconductor device comprising:

a circuit pattern formed over an insulating board;

a semiconductor chip bonded over the circuit pattern;

a connection conductor bonded to at least one of the circuit pattern and the semiconductor chip;

an insulating resin which exposes a welding portion of the connection conductor and which covers the circuit pattern and the semiconductor chip;

an external terminal which passes a main electric current through a main electrode of the semiconductor chip; and

an external connection conductor bonded to the external terminal and the welding portion of the connection conductor by laser welding.

6. The semiconductor device according to claim 5, further comprising an upper-layer insulating resin which covers an exposed portion of the connection conductor, the external terminal, and the external connection conductor over the insulating resin.

7. The semiconductor device according to claim 5, wherein:

the semiconductor chip includes one or more signal electrodes in addition to the main electrode; and

the insulating resin covers at least bonding wires which connect the one or more signal electrodes to signal terminals that draw out the one or more signal electrodes.

8. The semiconductor device according to claim 5, wherein the connection conductor has a bent structure in which there is a space between a side bonded to at least one of the circuit pattern and the semiconductor chip and the welding portion.

9. A method for fabricating a semiconductor device, the method comprising:

bonding a semiconductor chip to a circuit pattern formed over an insulating board;

bonding a connection conductor to at least one of the circuit pattern and the semiconductor chip;

exposing a welding portion of the connection conductor and covering the circuit pattern and the semiconductor chip with an insulating resin;

bonding an external terminal which passes a main electric current through a main electrode of the semiconductor chip to the welding portion of the connection conductor by laser welding after the exposing and the covering; and

injecting over the insulating resin an upper-layer insulating resin which covers an exposed portion of the connection conductor and the external terminal.

10. The method according to claim 9, wherein:

the insulating resin is a hardening resin;

the exposing and the covering includes hardening the hardening resin; and

removing foreign substances from a surface of the insulating resin is included before the injecting.

11. The method according to claim 9, wherein:

each of the insulating resin and the upper-layer insulating resin is a hardening resin and

hardening the insulating resin and the upper-layer insulating resin simultaneously is included after the injecting.

12. The method according to claim 9, wherein at least part of signal terminals electrically connected to signal electrodes of the semiconductor chip or bonding wires connected to the signal terminals are covered with the insulating resin.

13. A method for fabricating a semiconductor device, the method comprising:

bonding a semiconductor chip to a circuit pattern formed over an insulating board;

bonding a connection conductor to at least one of the circuit pattern and the semiconductor chip;

exposing a welding portion of the connection conductor and covering the circuit pattern and the semiconductor chip with an insulating resin;

bonding an external connection conductor to an external terminal which passes a main electric current through a main electrode of the semiconductor chip and the welding portion of the connection conductor by laser welding after the exposing and the covering; and

injecting over the insulating resin an upper-layer insulating resin which covers an exposed portion of the connection conductor, the external terminal, and the external connection conductor.

14. The method according to claim 13, wherein:

the insulating resin is a hardening resin;

the exposing and the covering includes hardening the hardening resin; and

removing foreign substances from a surface of the insulating resin is included before the injecting.

15. The method according to claim 13, wherein:

each of the insulating resin and the upper-layer insulating resin is a hardening resin and

hardening the insulating resin and the upper-layer insulating resin simultaneously is included after the injecting.

16. The method according to claim 13, wherein at least part of signal terminals electrically connected to signal electrodes of the semiconductor chip or bonding wires connected to the signal terminals are covered with the insulating resin.