SELF TESTING FAULT CIRCUIT APPARATUS AND METHOD

• US 20100295568A1
• Filed: 07/29/2010
• Published: 11/25/2010
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Leviton Manufacturing Company Incorporated
• Original Assignee: Leviton Manufacturing Company Incorporated
• Inventors: Ostrovsky, Michael, Kevelos, Adam
• Granted Patent: US 8,547,126 B2
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3277 of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
• CPC Class Codes: H02H 3/335 the main function being self testing of the device

Abstract

A self testing fault circuit interrupter device comprising a fault circuit comprising at least one line monitoring circuit, at least one line interrupting circuit and at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected. This fault circuit also includes at least one test circuit configured to initiate a self test on the fault circuit and at least one timing circuit for controlling the time period for a self test being performed on said at least one self test circuit. The timing circuitry can be in the form of external circuitry which comprises a transistor which controls the discharge rate of a timing capacitor. The timing capacitor is present to prevent any false triggering of a fault circuit. A fault circuit test condition does not stop until the capacitor is fully discharged. By controlling the timing capacitor discharge rate, the triggering of an SCR is not delayed too much in the presence of an external fault because during the presence of this external fault the test cycle is considerably shortened in time based directly upon the size of the external fault. The testing circuit can include a microcontroller which can be programmed to perform a self test across at least two different half cycles of opposite polarity. The determination of the timing of the self test is based upon timing performed by the microcontroller in combination with zero crossing circuitry.

Claims

1. A self testing fault circuit interrupter device comprising:

a) a fault circuit comprising;

i) at least one line monitoring circuit;

ii) at least one line interrupting circuit;

iii) at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected from said at least one line monitoring circuit;

b) at least one self test circuit configured to conduct a self test on said fault circuit; and

c) at least one timing circuit configured to control a duration of an output of said fault detector circuit.

2. The device as in claim 1, wherein said at least one self test circuit comprises at least one microcontroller.

3. The device as in claim 2, wherein said at least one self test circuit further comprises at least one transistor.

4. The device as in claim 3, wherein said at least one transistor is coupled to an output of said at least one microcontroller.

5. The device as in claim 1, wherein said at least one fault detector circuit comprises an integrated circuit.

6. The device as in claim 1, wherein said fault detection circuit further comprises at least one capacitor, wherein said timing circuit is configured to control a discharge rate of said capacitor.

7. The device as in claim 1, wherein said at least one fault detector circuit is an integrating fault detector circuit.

8. The device as in claim 1, wherein said timing circuit comprises at least one transistor, configured to selectively increase a discharge rate of said capacitor.

9. The device as in claim 8, wherein said timing circuit further comprises at least one resistor, wherein the resistance level of said resistor controls the rate of discharge of said capacitor.

10. The device as in claim 8, wherein said timing circuit is controlled by said microcontroller.

11. The device as in claim 1, further comprising at least one indicator circuit for communicating a result of a self test.

12. The device as in claim 11, wherein said at least one indicator is selected from the group consisting of an audible annunciator, a visible indicator, and a communication circuit.

13. The device as in claim 12, wherein said visible indicator comprises at least one LED.

14. The device as in claim 13, wherein said at least one LED is configured to display a plurality of self-test results.

15. The device as in claim 1, wherein said at least one line interrupting circuit comprises contacts, and wherein the device further comprises at least one contact detector circuit to detect whether said contacts are in an open or closed state.

16. The device as in claim 14, wherein said at least one LED is coupled to said contact detector circuit.

17. The device as in claim 15, wherein said self test circuit comprises a microcontroller, and wherein said at least one LED comprises a first LED coupled to said microcontroller, and a second LED coupled to said contact detector circuit.

18. The device as in claim 11, wherein said line interrupting circuit comprises contacts and said indicator circuit is configured to indicate at least one of the following states:

a) a first indication state indicating that either no power is provided to said fault circuit, and said self test circuit, or that a line and load wiring configuration has been reversed;

b) a second indication state indicating that there is no power provided to said self test circuit, and that at least one contact of said contacts has tripped;

c) a third indication state indicating that there is power provided to the device, that the self test has passed, and that at least one contact is latched;

d) a fourth indication state indicating that there is power provided to the device, that the self test has passed, and that at least one contact is open;

e) a fifth indication state indicating that said self test has failed, and indicating that at least one contact did not open successfully; and

f) a sixth indication state indicating that said self test has failed and that at least one contact has opened.

19. The device as in claim 2, further comprising zero crossing circuitry in communication with said microcontroller, wherein said microcontroller in combination with said zero crossing circuitry forms said line monitoring circuit which is configured to sense an output of said zero crossing circuitry to determine an over voltage or an under voltage condition.

20. The device as in claim 1, wherein said at least one self test circuit is configured to provide a simulated fault signal during at least a portion of a first half cycle and during at least a portion of a second half cycle of opposite polarity.

21. The device as in claim 2, further comprising at least one overcurrent detector, wherein said microcontroller is configured to perform at least one of the following steps:

activating said at least one line interrupting circuit when said microcontroller determines an overcurrent condition; and

indicating an overcurrent condition when said microcontroller determines an overcurrent condition.

22. The device as in claim 2, further comprising at least one temperature sensor coupled to said microcontroller, wherein said microcontroller is configured to activate said at least one line interrupting circuit when said microcontroller determines a temperature has crossed a preset threshold point.

23. The device as in claim 2, further comprising at least one fuse coupled to said microcontroller, and to at least one of a phase line or a neutral line, wherein said microcontroller is configured to selectively open a path on said phase line or said neutral line by actuating said fuse.

24. The device as in claim 2, wherein said at least one fault detection circuit comprises an integrated circuit, wherein said microcontroller is configured to conduct a self test during at least a portion of a positive half cycle and during at least a portion of a negative half cycle of AC current.

25. The device as in claim 1, wherein said at least one line monitoring circuit comprises at least one sensor.

26. The self testing fault circuit interrupter device as in claim 2, further comprising:

at least one temperature sensor, which is in communication with said microcontroller, wherein said microcontroller is configured to actuate said line interrupting circuit.

27. The device as in claim 26, further comprising:

a line side coupled to a set of building wiring, providing power to the device;

a load side coupled to a downstream load,

a plurality of selectively separable contacts configured to electrically connect/disconnect said line side from said load side;

wherein said microcontroller is configured to actuate said line interrupting circuit.

28. The self testing fault circuit interrupter device as in claim 19, wherein a level of overvoltage is determined based on a slope of the zero crossing output.

29. The self testing fault circuit interrupter device as in claim 27, wherein said microcontroller upon determining an overvoltage condition is configured to perform at least one of the following tasks:

indicate an overvoltage condition;

actuate he at least one line interrupting circuit.

30. The self testing fault circuit interrupter device as in claim 14 wherein said at least one LED comprises a plurality of LEDs and wherein said display of a plurality of test results comprises a display of:

at least one of;

all of said plurality of LEDS off, at least one LED of said plurality of LEDs on;

at least two of said plurality of LEDs on;

all LEDs on;

at least one LED blinking;

31. A self testing fault circuit interrupter device comprising:

a) a fault circuit;

b) at least one self test circuit for initiating a self test on said fault circuit wherein said at least one self test circuit comprises;

i) at least one microcontroller;

ii) at least one timing circuit, configured to control the time period of the self test, and to shorten the time period for the self test in the presence of an actual fault.

32. A self testing fault circuit interrupter device comprising:

a) a fault circuit;

b) at least one self test means for initiating a self test on said fault circuit, during at least a portion of a positive half cycle and during at least a portion of a negative half cycle of AC current.

33. The self testing device as in claim 32, further comprising a circuit interrupting means which is selectively activated by said self test means when said self test means determines that there is a failed self test condition.

34. A self testing fault circuit interrupter device comprising:

a) a plurality of components comprising at least one of fault detecting components, and interrupter components;

b) a testing circuit for testing at least one of said components of said plurality of fault detecting components or said interrupter components, said testing circuit having at least one circuit configured to control a self test time duration; and

c) an indicator connected to the testing circuit for providing an indication of whether a self test has failed.

76. The device as in claim 34, wherein said fault detecting components comprise at least one of a transformer, a microcontroller, and a fault circuit.

77. The device as in claim 34 wherein said interrupter components comprise at least one of a SCR, a solenoid, and separatable contacts.

35. A process for self testing a fault circuit comprising:

a) disabling an actuator;

b) performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity; and

c) determining whether the self test was successful.

36. The process as in claim 35, wherein said step of disabling said actuator comprises preventing a signal from reaching said actuator.

37. The process as in claim 36, wherein said step of disabling said actuator comprises blocking a SCR from receiving a fault signal.

38. The process as in claim 35, wherein said step of performing a self test comprises creating a current imbalance between a phase and neutral line.

39. The process as in claim 35, wherein said step of performing a self test comprises:

creating a current imbalance by activating at least one transistor to cause current to flow from at least one electrical conductor configured to be read by at least one fault sensor, wherein said current imbalance is read by said at least one fault sensor.

40. The process as in claim 35, wherein said step of performing a self test comprises:

a) detecting a zero crossing of an AC line signal;

b) timing a self test to occur during at least a portion of a first half cycle of a first polarity and during at least a portion of a second half cycle of opposite polarity.

41. The process as in claim 40, further comprising the step of timing a self test during an alternate half cycle of alternating current.

42. The process as in claim 41, wherein said step of timing a self test during at least one half cycle of alternating current comprises timing a self test during only a portion of said at least one half cycle of alternating current.

43. The process as in claim 35, further comprising the step of controlling a duration of a self test.

44. The process as in claim 43, wherein said step of controlling a duration of a self test comprises controlling said duration based upon an amount of power fed into a capacitor.

45. The process as in claim 44, wherein said step of controlling a duration of a self test comprises controlling a discharge rate of power of said capacitor.

46. The process as in claim 35, wherein said step of detecting a fault includes receiving a signal from a fault sensor indicating the presence of a fault.

47. The process as in claim 35, wherein said step of indicating a result of said self test comprises providing a light indication for said self test.

48. The process as in claim 35, wherein said step of indicating a result of said self test comprises providing an audio indication for said self test.

49. The process as in claim 35, wherein said step of indicating a result of said self test comprises indicating whether a self test is performed successfully.

50. The process as in claim 35, wherein said step of indicating a result of said self test comprises indicating whether a set of contacts have tripped.

51. The process as in claim 35, further comprising the step of determining an overcurrent condition.

52. The process as in claim 35, further comprising the step of determining an overvoltage condition.

53. The process as in claim 35, further comprising the step of permanently removing the fault circuit from operation by opening a fusable link along at least one of said phase line and said neutral line.

54. The process as in claim 43, further comprising the step of controlling a duration of the self test based upon the presence of an external fault.

55. The process as in claim 54, wherein said step of controlling the duration of the self test comprises receiving an external fault comprising a ground fault.

56. The process as in claim 55, wherein said step of controlling a duration of a self test comprises removing power from a capacitor.

57. The process as in claim 56, wherein said step of receiving an external fault comprises providing power from said external fault to said capacitor to reduce a time for completing said step of performing a self test.

58. The process as in claim 56, further comprising the step of actuating an actuator to remove power to a load side when an external fault exists beyond said step of providing a self test.

59. The process as in claim 43, further comprising the step of determining when a fault signal is received to determine whether an external fault is occurring.

60. The process as in claim 59, further comprising the step of actuating said actuator to remove power to a load side in response to determining that an external fault exists.

61. The process as in claim 43, further comprising the step of activating a transistor to control the duration of a self test.

62. The process as in claim 61, wherein said step of activating a transistor, comprises turning a transistor on, and wherein the process further includes the step of discharging a capacitor, wherein said step of turning a transistor on, creates a discharge path for said capacitor, to create a shorter test cycle.

63. The process as in claim 62, wherein after said step of discharging a capacitor is completed, said step of disabling an actuator is completed.

68. The self testing fault circuit interrupter as in claim 60, wherein said microcontroller is configured to determine the level of undervoltage based a slope of a zero crossing AC line.

64. A self testing fault circuit interrupter device comprising:

a) at least one line side;

b) at least one load side;

c) a fault circuit comprising;

i) at least one line monitoring circuit;

ii) at least one line interrupting circuit;

iii) at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected from said at least one line monitoring circuit;

d) at least one self test circuit configured to conduct a self test on said fault circuit;

e) at least one microcontroller which is configured to selectively operate said self test circuit;

f) at least one temperature sensor, which is in communication with said microcontroller, wherein said microcontroller is configured to open said line interrupting circuit to electrically disconnect said line side from said load side.

65. The self testing fault circuit interrupter as in claim 64, further comprising an overvoltage sensor comprising:

i) said microcontroller; and

ii) zero crossing circuitry, wherein said microcontroller is configured to read said zero crossing circuitry.

66. The self testing fault circuit interrupter as in claim 65, wherein said microcontroller is configured to determine the level of overvoltage based on a slope of a zero crossing AC line.

67. The self testing fault circuit interrupter as in claim 65, wherein said microcontroller upon determining an overvoltage condition is configured to perform at least one of the following tasks:

indicate an overvoltage condition;

activate the at least one line interrupting circuit to disconnect a line side from a load side;

permanently disconnecting the line side from the load side.

69. A self test circuit comprising:

a) a self test circuit configured to create an imbalance signal;

b) a fault circuit, configured to send a fault signal after detecting said imbalance signal;

c) an indicator circuit having an input in communication with an output of said fault circuit;

wherein said self test circuit is configured to prevent said fault signal from activating said indicator circuit.

70. The self test circuit as in claim 69, wherein said self test circuit is configured to create a low output state, to prevent said fault signal from activating said indicator circuit.

71. A method for testing a fault circuit comprising the following steps:

a) periodically preventing an actuator from activating;

b) activating a self test by creating a current imbalance, which occurs across at least two different half cycles of opposite polarity;

c) testing a fault circuit by reading said current imbalance.

72. A self-testing fault circuit interrupter comprising a ground fault detector, and a self testing circuit, the self testing circuit comprising:

at least one controller configured to emit a circuit hinder signal to hinder a breaking signal from said ground fault detector,

at least one controller adapted to periodically output a test signal simulating a ground fault; and

an alarm circuit adapted to receive an output signal from the ground fault detector in response to detecting the ground fault, and adapted to output an alarm when the ground fault detector is not operative.

73. The self testing fault circuit as in claim 72, further comprising a microcontroller which comprises said at least one controller configured to emit a circuit hinder signal and said at least one controller adapted to periodically output a test signal.

74. A ground fault circuit interrupter system, comprising:

a ground fault detector circuit;

a signal circuit electrically coupled to the ground fault detector circuit and configured to output a circuit hinder signal to inhibit a breaking signal from the ground fault detector, the signal circuit also for outputting a test signal to the ground fault detector; and

an alarm circuit electrically coupled to the ground fault detector and for receiving an output signal from the ground fault detector in response to the test signal.

75. A method for testing a fault circuit comprising:

periodically outputting a circuit hinder signal to hinder a disconnect signal from a fault detector circuit, the circuit hinder signal being output at a first period of time;

outputting a test signal to said fault detector circuit only if the circuit hinder signal is output, the test signal testing said fault detector circuit;

receiving from said fault detector circuit an output signal in response to the test signal when said fault detector is operative; and

activating an alarm during a second period of time if the output signal is not received during said first period of time.