SELF TESTING FAULT CIRCUIT APPARATUS AND METHOD
First Claim
1. A self testing fault circuit interrupter device comprising:
- a) a fault circuit comprising;
i) at least one line monitoring circuit;
ii) at least one line interrupting circuit;
iii) at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected from said at least one line monitoring circuit;
b) at least one self test circuit configured to conduct a self test on said fault circuit; and
c) at least one timing circuit configured to control a duration of an output of said fault detector circuit.
1 Assignment
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Accused Products
Abstract
A self testing fault circuit interrupter device comprising a fault circuit comprising at least one line monitoring circuit, at least one line interrupting circuit and at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected. This fault circuit also includes at least one test circuit configured to initiate a self test on the fault circuit and at least one timing circuit for controlling the time period for a self test being performed on said at least one self test circuit. The timing circuitry can be in the form of external circuitry which comprises a transistor which controls the discharge rate of a timing capacitor. The timing capacitor is present to prevent any false triggering of a fault circuit. A fault circuit test condition does not stop until the capacitor is fully discharged. By controlling the timing capacitor discharge rate, the triggering of an SCR is not delayed too much in the presence of an external fault because during the presence of this external fault the test cycle is considerably shortened in time based directly upon the size of the external fault. The testing circuit can include a microcontroller which can be programmed to perform a self test across at least two different half cycles of opposite polarity. The determination of the timing of the self test is based upon timing performed by the microcontroller in combination with zero crossing circuitry.
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Citations
77 Claims
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1. A self testing fault circuit interrupter device comprising:
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a) a fault circuit comprising; i) at least one line monitoring circuit; ii) at least one line interrupting circuit; iii) at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected from said at least one line monitoring circuit; b) at least one self test circuit configured to conduct a self test on said fault circuit; and c) at least one timing circuit configured to control a duration of an output of said fault detector circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A self testing fault circuit interrupter device comprising:
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a) a fault circuit; b) at least one self test circuit for initiating a self test on said fault circuit wherein said at least one self test circuit comprises; i) at least one microcontroller; ii) at least one timing circuit, configured to control the time period of the self test, and to shorten the time period for the self test in the presence of an actual fault.
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32. A self testing fault circuit interrupter device comprising:
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a) a fault circuit; b) at least one self test means for initiating a self test on said fault circuit, during at least a portion of a positive half cycle and during at least a portion of a negative half cycle of AC current. - View Dependent Claims (33)
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34. A self testing fault circuit interrupter device comprising:
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a) a plurality of components comprising at least one of fault detecting components, and interrupter components; b) a testing circuit for testing at least one of said components of said plurality of fault detecting components or said interrupter components, said testing circuit having at least one circuit configured to control a self test time duration; and c) an indicator connected to the testing circuit for providing an indication of whether a self test has failed. - View Dependent Claims (76, 77)
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35. A process for self testing a fault circuit comprising:
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a) disabling an actuator; b) performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity; and c) determining whether the self test was successful. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 68)
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64. A self testing fault circuit interrupter device comprising:
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a) at least one line side; b) at least one load side; c) a fault circuit comprising; i) at least one line monitoring circuit; ii) at least one line interrupting circuit; iii) at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected from said at least one line monitoring circuit; d) at least one self test circuit configured to conduct a self test on said fault circuit; e) at least one microcontroller which is configured to selectively operate said self test circuit; f) at least one temperature sensor, which is in communication with said microcontroller, wherein said microcontroller is configured to open said line interrupting circuit to electrically disconnect said line side from said load side. - View Dependent Claims (65, 66, 67)
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69. A self test circuit comprising:
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a) a self test circuit configured to create an imbalance signal; b) a fault circuit, configured to send a fault signal after detecting said imbalance signal; c) an indicator circuit having an input in communication with an output of said fault circuit; wherein said self test circuit is configured to prevent said fault signal from activating said indicator circuit. - View Dependent Claims (70)
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71. A method for testing a fault circuit comprising the following steps:
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a) periodically preventing an actuator from activating; b) activating a self test by creating a current imbalance, which occurs across at least two different half cycles of opposite polarity; c) testing a fault circuit by reading said current imbalance.
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72. A self-testing fault circuit interrupter comprising a ground fault detector, and a self testing circuit, the self testing circuit comprising:
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at least one controller configured to emit a circuit hinder signal to hinder a breaking signal from said ground fault detector, at least one controller adapted to periodically output a test signal simulating a ground fault; and an alarm circuit adapted to receive an output signal from the ground fault detector in response to detecting the ground fault, and adapted to output an alarm when the ground fault detector is not operative. - View Dependent Claims (73)
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74. A ground fault circuit interrupter system, comprising:
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a ground fault detector circuit; a signal circuit electrically coupled to the ground fault detector circuit and configured to output a circuit hinder signal to inhibit a breaking signal from the ground fault detector, the signal circuit also for outputting a test signal to the ground fault detector; and an alarm circuit electrically coupled to the ground fault detector and for receiving an output signal from the ground fault detector in response to the test signal.
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75. A method for testing a fault circuit comprising:
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periodically outputting a circuit hinder signal to hinder a disconnect signal from a fault detector circuit, the circuit hinder signal being output at a first period of time; outputting a test signal to said fault detector circuit only if the circuit hinder signal is output, the test signal testing said fault detector circuit; receiving from said fault detector circuit an output signal in response to the test signal when said fault detector is operative; and
activating an alarm during a second period of time if the output signal is not received during said first period of time.
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Specification