GRAPHICS PROCESSING SYSTEM WITH POWER-GATING CONTROL FUNCTION, POWER-GATING CONTROL METHOD, AND COMPUTER PROGRAM PRODUCTS THEREOF

• US 20100295852A1
• Filed: 09/29/2009
• Published: 11/25/2010
• Est. Priority Date: 05/25/2009
• Status: Active Grant

• Current Assignee: Institute For Information Industry
• Original Assignee: Institute For Information Industry
• Inventors: Cheng, Yu-Jung, YANG, Chia-Lin, Wang, Po-Han
• Granted Patent: US 8,570,332 B2
• Time in Patent Office: Days
• US Class Current: 345/426
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.

Claims

1. A power-gating control method for a graphics processing unit having a unified shader unit, which comprises a plurality of shaders, comprising:

rendering a plurality of previous frames;

calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame;

determining a second number of active shaders for rendering a next frame immediately following the previous frames according to the first number of active shaders and the corresponding frame rate of each previous frame; and

activating corresponding shaders through one or more power-gating control elements according the second number of active shaders.

2. The power-gating control method as claimed in claim 1, further comprising:

rendering the next frame by use of the activated shaders.

3. The power-gating control method as claimed in claim 1, further comprising:

executing a first application program; and

calculating the first number of active shaders and the corresponding frame rate of each previous frame in response to the execution of the first application program, wherein the first application program corresponds to the end of each previous frame.

4. The power-gating control method as claimed in claim 1, wherein determining the second number of active shaders comprises:

obtaining a power state of each shader prior to determining the second number of active shaders.

5. The power-gating control method as claimed in claim 4, wherein activating the corresponding shaders comprises:

executing a second application program; and

generating a command packet in response to the execution of the second application program according to the second number of active shaders and the power state of each shader, for controlling the one or more power-gating control elements,

wherein the second application program corresponds to the start of the next frame.

6. The power-gating control method as claimed in claim 5, further comprising:

generating one or more control signals in response to the command packet,

wherein each power-gating control element is turned on or turned off by a corresponding control signal.

7. The power-gating control method as claimed in claim 6, wherein each power-gating control element comprises a transistor coupled between a voltage source and at least one shader, and the transistor determines whether the at least one shader is supplied by the voltage source according to the corresponding control signal.

8. The power-gating control method as claimed in claim 1, wherein the shaders comprise a plurality of shader clusters coupled to a plurality of texture units, each texture unit is coupled to at least one shader cluster, and each power-gating control element activates a texture unit and the at least one shader cluster coupled thereto.

9. The power-gating control method as claimed in claim 1, wherein the second number of active shaders is generated by the following formula:

10. A graphics processing system with power-gating control function comprising:

a graphics processing unit, comprising a unified shader unit and one or more power-gating control elements, wherein the unified shader unit comprises a plurality of shaders for rendering a plurality of previous frames and the one or more power-gating control elements are coupled to the shaders; and

a driver coupled to the graphics processing unit for calculating a first number of active shaders for rendering each previous frame and a corresponding frame rate of each previous frame, and determining a second number of active shaders for rendering a next frame immediately following the previous frames according to the first number of active shaders and the corresponding frame rate of each previous frame,

wherein the one or more power-gating control elements activate corresponding shaders according to the second number of active shaders.

11. The graphics processing system as claimed in claim 10, wherein the graphics processing system renders the next frame by use of the activated shaders.

12. The graphics processing system as claimed in claim 10, wherein when a first application program is executed, in response to the execution of the first application program, the driver calculates the first number of active shaders and the corresponding frame rate of each previous frame, and the first application program corresponds to the end of each previous frame.

13. The graphics processing system as claimed in claim 10, wherein the driver obtains a power state of each shader prior to determining the second number of active shaders.

14. The graphics processing system as claimed in claim 13, wherein when a second application program is executed, in response to the execution of the second application program, the driver generates a command packet according the second number of active shaders and the power state of each shader, for controlling the one or more power-gating control elements, and the second application program corresponds to the start of the next frame.

15. The graphics processing system as claimed in claim 14, wherein the graphics processing unit comprises:

a command processor coupled to the driver for generating one or more control signals in response to the command packet,

wherein each power-gating control element is turned on or turned off by a corresponding control signal.

16. The graphics processing system as claimed in claim 15, wherein each power-gating control element comprises a transistor coupled between a voltage source and at least one shader the transistor determines whether the at least one shader is supplied by the voltage source according to the corresponding control signal.

17. The graphics processing system as claimed in claim 10, wherein the shaders comprises a plurality of shader clusters coupled to a plurality of texture units, each texture unit is coupled to at least one shader cluster, and each power-gating control element activates a texture unit and the at least one shader cluster coupled thereto.

18. The graphics processing system as claimed in claim 10, wherein the second number of active shaders is generated by the following formula:

19. A computer program product loaded into and executed by a machine to perform a power-gating control method for a graphics processing unit having a unified shader unit, which comprises a plurality of shaders, the computer program product comprising:

a first program code for rendering a plurality of previous frames;

a second program code for calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame;

a third program code for determining a second number of active shaders for rendering a next frame immediately following the previous frames according the first number of active shaders and the corresponding frame rate of each previous frame; and

a fourth program code for activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.

20. The computer program product as claimed in claim 19, wherein the shaders comprise a plurality of shader clusters coupled to a plurality of texture units, each texture unit is coupled to at least one shader cluster, and each power-gating control element activates a texture unit and the at least one shader cluster coupled thereto.

21. The computer program product as claimed in claim 19, wherein the second number of active shaders is generated by the following formula: