THIN FILM TRANSISTOR ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY

• US 20100296018A1
• Filed: 07/30/2010
• Published: 11/25/2010
• Est. Priority Date: 05/16/2001
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KIM, Dong-Gyu
• Granted Patent: US 8,736,780 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136268 Switch defects
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

A thin film transistor array substrate for a liquid crystal display includes a substrate, and a gate line assembly formed on the substrate to receive gate signals. The gate line assembly has gate lines proceeding in the horizontal direction, and gate electrodes connected to the gate lines. A storage capacitor line assembly proceeds in the horizontal direction. A gate insulating layer is formed on the substrate while covering the gate lines and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer over the gate electrodes. A data line assembly is formed on the gate insulating layer. The data line assembly has data lines crossing over the gate lines to define pixel regions, source electrodes connected to the data lines while being placed on the semiconductor pattern, and drain electrodes facing the source electrodes around the gate electrodes while being placed on the semiconductor pattern. A protective layer covers the data line assembly and the semiconductor pattern with contact holes. Pixel electrodes are formed on the protective layer at the respective pixel regions such that the pixel electrodes are connected to the drain electrodes through the contact holes. The gate lines or the pixel electrodes are provided with repair members, and the repair members are partially overlapped with the front gate lines or the pixel electrodes.

Claims

1. A thin film transistor array panel comprising:

a substrate;

a first gate line disposed on the substrate;

a second gate line disposed adjacent to the first gate line;

a data line crossing the first and the second gate lines;

a thin film transistor electrically connected to the second gate line and the data line respectively;

a pixel electrode electrically connected to the thin film transistor and comprising an extended portion, the extended portion overlapping the first gate line; and

a storage capacitance wire disposed between the first and the second gate lines, and overlapping the pixel electrode.

2. The thin film transistor array panel of claim 1, wherein the second gate line is electrically connected to the thin film transistors of (n)th row of the array, and the first gate line is electrically connected to the thin film transistors of (n−

1)th row of the array.

3. The thin film transistor array panel of claim 2, wherein the storage capacitance wire comprises:

a first portion parallel to the first and the second gate lines; and

a second portion extended from the first portion, and parallel to the data line.

4. The thin film transistor array panel of claim 3, wherein the first portion fully overlaps the pixel electrode.

5. The thin film transistor array panel of claim 4, wherein the second portion overlaps at least one edge of the pixel electrode.

6. The thin film transistor array panel of claim 5, wherein the second portion overlaps two opposing edges of the pixel electrode.

7. The thin film transistor array panel of claim 1, wherein a semiconductor pattern of the thin film transistor lies within edges of the second gate line

8. A thin film transistor array panel comprising:

a substrate;

a first gate line disposed on the substrate;

a second gate line disposed next to the first gate line;

a data line crossing the first and the second gate lines;

a thin film transistor electrically connected to the second gate line and the data line respectively;

a pixel electrode electrically connected to the thin film transistor and comprising an extended portion, the extended portion overlapping the first gate line; and

a storage capacitance wire disposed between the first and the second gate lines, and overlapping the pixel electrode,

wherein the storage capacitance wire comprises;

a first portion parallel to the first and the second gate lines; and

a second portion extended from the first portion, and parallel to the data line.

9. The thin film transistor array panel of claim 8, wherein the first portion fully overlaps the pixel electrode.

10. The thin film transistor array panel of claim 9, wherein the second portion overlaps at least one edge of the pixel electrode.

11. The thin film transistor array panel of claim 10, wherein the second portion overlaps two opposing edges of the pixel electrode.

12. The thin film transistor array panel of claim 8, wherein a semiconductor pattern of the thin film transistor lies within edges of the second gate line.

13. A liquid crystal display device comprising:

a first substrate comprising a common electrode;

a second substrate opposing the first substrate with a liquid crystal layer therebetween, the second substrate comprising;

a first gate line disposed on the second substrate;

a second gate line disposed next to the first gate line;

a data line crossing the first and the second gate lines;

a thin film transistor electrically connected to the second gate line and the data line respectively;

a pixel electrode opposing the common electrode, and electrically connected to the thin film transistor, the pixel electrode comprising an extended portion overlapping the first gate line; and

a storage capacitance wire disposed between the first and the second gate lines, and overlapping the pixel electrode,

wherein the device shows white display when no voltage is applied to the pixel electrode.

14. The liquid crystal display device of claim 13, wherein the storage capacitance wire comprises:

a first portion parallel to the first and the second gate lines; and

a second portion extended from the first portion, and parallel to the data line.

15. The liquid crystal display device of claim 14, wherein the first portion fully overlaps the pixel electrode.

16. The liquid crystal display device of claim 15, wherein the second portion overlaps at least one edge of the pixel electrode.

17. The liquid crystal display device of claim 16, wherein the second portion overlaps two opposing edges of the pixel electrode.

18. The liquid crystal display device of claim 13, wherein a semiconductor pattern of the thin film transistor lies within edges of the second gate line.