Differential Plate Line Screen Test for Ferroelectric Latch Circuits

• US 20100296329A1
• Filed: 05/17/2010
• Published: 11/25/2010
• Est. Priority Date: 05/21/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bartling, Steven Craig, McAdams, Hugh P., Rodriguez, John Anthony, Summerfelt, Scott R.
• Granted Patent: US 8,416,598 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

Claims

1. A method of testing a non-volatile latch circuit in an integrated circuit, the latch circuit comprising cross-coupled inverters driving first and second storage nodes, a first ferroelectric capacitor having a first plate coupled to the first storage node, and a second ferroelectric capacitor having a first plate coupled to the second storage node, the method comprising:

setting the state of the latch circuit so that the first and second storage nodes are at low and high logic states, respectively;

then polarizing the first and second ferroelectric capacitors to opposite polarization states, corresponding to the state of the latch circuit, by applying low and high bias voltages to a second plate of the first ferroelectric capacitor and a second plate of the second ferroelectric capacitor;

then removing bias from the cross-coupled inverters of the latch circuit;

then biasing the second plate of the first ferroelectric capacitor to a first bias voltage, and biasing the second plate of the second ferroelectric capacitor to a second bias voltage, the second bias voltage lower than the first bias voltage by a selected differential;

then applying bias to the cross-coupled inverters of the latch circuit; and

then reading the state of the latch circuit.

2. The method of claim 1, wherein the latch circuit further comprises a third ferroelectric capacitor having a first plate coupled to the first storage node and a second plate coupled to a second plate line, and a fourth ferroelectric capacitor having a first plate coupled to the second storage node and a second plate coupled to the second plate line;

and wherein the method further comprises;

during the polarizing step, applying low and high bias voltages to the second plate line; and

during the biasing step, applying a ground voltage to the second plate line.

3. The method of claim 1, wherein the latch circuit corresponds to a static random access memory cell, the memory cell further comprising first and second pass gates having a conduction path coupled between the first and second storage nodes and first and second complementary bit lines, respectively, and having a control terminal receiving a word line;

and wherein the method further comprises;

turning off the first and second pass gates during the biasing step.

4. The method of claim 3, wherein the reading step comprises:

turning on the first and second pass gates;

sensing a differential signal from the first and second complementary bit lines; and

communicating a logic signal corresponding to the sensed differential signal.

5. The method of claim 1, wherein the latch circuit corresponds to a stage in a logic circuit, the logic circuit further comprising a first stage having an output coupled to one of the first and second sense nodes, and a second stage having an input coupled to one of the first and second sense nodes;

wherein the method further comprises;

isolating the first and second sense nodes from the first and second stages during the biasing step;

and wherein the reading step comprises;

driving an output logic level from the second stage corresponding to the state of the latch circuit.

6. The method of claim 1, further comprising:

setting the state of the latch circuit so that the first and second storage nodes are at high and low logic states, respectively;

then polarizing the first and second ferroelectric capacitors by applying low and high bias voltages to each of the second plates of the first and second ferroelectric capacitors;

then removing bias from the cross-coupled inverters of the latch circuit;

then biasing the second plate of the first ferroelectric capacitor to the second bias voltage, and biasing the second plate of the second ferroelectric capacitor to the first bias voltage, the second bias voltage lower than the first bias voltage by the selected differential;

then applying bias to the cross-coupled inverters of the latch circuit; and

then reading the state of the latch circuit.

7. The method of claim 1, further comprising:

after the step of removing bias and before the step of then biasing the second plate of the first ferroelectric capacitor, stressing the integrated circuit.

8. The method of claim 7, wherein the stressing step comprises:

baking the integrated circuit at an elevated temperature for a selected duration.

9. The method of claim 8, further comprising:

after the reading step, setting the state of the latch circuit so that the first and second storage nodes are at high and low logic states, respectively;

then polarizing the first and second ferroelectric capacitors by applying low and high bias voltages to each of the second plates of the first and second ferroelectric capacitors;

then removing bias from the cross-coupled inverters of the latch circuit;

then biasing the second plate of the first ferroelectric capacitor to the second bias voltage, and biasing the second plate of the second ferroelectric capacitor to the first bias voltage, the second bias voltage lower than the first bias voltage by a second selected differential;

then applying bias to the cross-coupled inverters of the latch circuit; and

then reading the state of the latch circuit.

10. The method of claim 8, further comprising:

after the reading step, setting the state of the latch circuit so that the first and second storage nodes are at high and low logic states, respectively;

then polarizing the first and second ferroelectric capacitors by applying low and high bias voltages to each of the second plates of the first and second ferroelectric capacitors;

then removing bias from the cross-coupled inverters of the latch circuit;

then baking the integrated circuit at an elevated temperature for a selected duration;

then biasing the second plate of the first ferroelectric capacitor to the second bias voltage, and biasing the second plate of the second ferroelectric capacitor to the first bias voltage, the second bias voltage lower than the first bias voltage by the selected differential;

then applying bias to the cross-coupled inverters of the latch circuit; and

then reading the state of the latch circuit.

11. A method of screening non-volatile latch circuits, each latch circuit comprising cross-coupled inverters driving first and second storage nodes, a first ferroelectric capacitor having a first plate coupled to the first storage node, and a second ferroelectric capacitor having a first plate coupled to the second storage node, the method comprising:

characterizing each of a plurality of latch circuits by performing a plurality of operations comprising;

setting the state of the latch circuit so that the first and second storage nodes are at low and high logic states, respectively;

then polarizing the first and second ferroelectric capacitors to opposite polarization states, corresponding to the state of the latch circuit, by applying low and high bias voltages to a second plate of the first ferroelectric capacitor and a second plate of the second ferroelectric capacitor;

then removing bias from the cross-coupled inverters of the latch circuit;

then biasing the second plate of the first ferroelectric capacitor to a first bias voltage, and biasing the second plate of the second ferroelectric capacitor to a second bias voltage, the second bias voltage lower than the first bias voltage by a differential voltage;

then applying bias to the cross-coupled inverters of the latch circuit;

then reading the state of the latch circuit;

adjusting the differential voltage; and

repeating the setting, polarizing, removing, biasing, applying, reading, and adjusting operations to determine a fail differential voltage that causes the reading operation to sense a state of the latch circuit opposite from that set in the setting step;

stressing the plurality of latch circuits;

evaluating the stressed plurality of latch circuits; and

then determining a screen differential voltage from the evaluated plurality of latch circuits.

12. The method of claim 11, wherein the evaluating step comprises, for each of the plurality of latch circuits:

polarizing the first and second ferroelectric capacitors to set a programmed state in each of the plurality of latch circuits;

removing bias from the cross-coupled inverters of the latch circuit;

then biasing the second plates of the first and second ferroelectric capacitors to restore a state to the latch circuit;

then applying bias to the cross-coupled inverters of the latch circuit;

then reading the state of the latch circuit; and

comparing the read state with the programmed state;

and wherein the step of determining the screen differential voltage comprises;

identifying, from the testing step, those latch circuits for which the stressing step caused loss of the programmed state; and

identifying a screen differential voltage from the fail differential voltages of the identified latch circuits.

13. The method of claim 12, wherein the plurality of latch circuits each correspond to a flip-flop in a logic circuit, the logic circuit further comprising a first stage having an output coupled to one of the first and second sense nodes, and a second stage having an input coupled to one of the first and second sense nodes;

wherein the characterizing step further comprises;

isolating the first and second sense nodes from the first and second stages during the biasing step;

and wherein the reading operation comprises;

driving an output logic level from the second stage corresponding to the state of the latch circuit.

14. The method of claim 11, further comprising:

determining a pre-stress distribution of the fail differential voltages;

wherein the evaluating step comprises;

determining a post-stress fail differential voltage for each of the stressed plurality of latch circuits;

and wherein the step of determining the screen differential voltage comprises;

determining a post-stress distribution of the post-stress fail differential voltages; and

identifying a screen differential voltage from a comparison of the pre-stress and post-stress fail differential voltage distributions.

15. The method of claim 11, wherein the stressing step comprises:

baking the plurality of latch circuits.

16. The method of claim 11, wherein each latch circuit further comprises a third ferroelectric capacitor having a first plate coupled to the first storage node and a second plate coupled to a second plate line, and a fourth ferroelectric capacitor having a first plate coupled to the second storage node and a second plate coupled to the second plate line;

and wherein the characterizing step further comprises;

during the polarizing operation, applying low and high bias voltages to the second plate line; and

during the biasing operation, applying a ground voltage to the second plate line.

17. The method of claim 11, wherein the plurality of latch circuits each correspond to a static random access memory cell, the memory cell further comprising first and second pass gates having a conduction path coupled between the first and second storage nodes and first and second complementary bit lines, respectively, and having a control terminal receiving a word line;

and wherein the characterizing step further comprises;

turning off the first and second pass gates during the biasing operation.

18. The method of claim 17, wherein the reading operation comprises:

turning on the first and second pass gates;

activating a sense amplifier to sense a differential signal from the first and second complementary bit lines; and

communicating a logic signal corresponding to the sensed differential signal.

19. The method of claim 11, wherein the plurality of latch circuits are disposed in a plurality of integrated circuits.

20. An integrated circuit, comprising:

at least one latch circuit comprising;

cross-coupled inverters driving first and second storage nodes;

a first ferroelectric capacitor having a first plate coupled to the first storage node and a second plate; and

a second ferroelectric capacitor having a first plate coupled to the second storage node and a second plate;

input circuitry for setting the state of the at least one latch circuit;

output circuitry for sensing the state of the at least one latch circuit;

a first plate line coupled to the second plate of the first ferroelectric capacitor;

a second plate line coupled to the second plate of the second ferroelectric capacitor; and

plate line driver circuitry for applying low and high bias voltages to each of the second plates of the first and second ferroelectric capacitors to polarize the first and second ferroelectric capacitors to opposite polarization states, corresponding to the state of the latch circuit, and for biasing, in a test operation, a first bias voltage to the second plate of the first ferroelectric capacitor and a second bias voltage to the second plate of the second ferroelectric capacitor, the second bias voltage lower than the first bias voltage by a selected differential.

21. The integrated circuit of claim 20, wherein the at least one latch circuit further comprises:

a third ferroelectric capacitor having a first plate coupled to the first storage node and a second plate coupled to a second plate line; and

a fourth ferroelectric capacitor having a first plate coupled to the second storage node and a second plate coupled to the second plate line;

and wherein the plate line driver circuitry is also for applying low and high bias voltages to the second plate line to polarize the third and fourth ferroelectric capacitors, and is also for biasing, in the test operation, the second plate line to a ground voltage.

22. The integrated circuit of claim 20, wherein the latch circuit corresponds to a static random access memory cell, the memory cell further comprising first and second pass gates having a conduction path coupled between the first and second storage nodes and first and second complementary bit lines, respectively, and having a control terminal receiving a word line;

and further comprising;

word line drivers for selectively turning the first and second pass gates on and off;

read/write circuitry, coupled to the first and second bit lines.

23. The integrated circuit of claim 20, wherein the latch circuit corresponds to a flip-flop in a logic circuit.