SEMICONDUCTOR MEMORY DEVICE

• US 20100296330A1
• Filed: 05/11/2010
• Published: 11/25/2010
• Est. Priority Date: 05/19/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Wakaiki, Syuji, KOTAKI, Hiroshi, Ohta, Yoshiji
• Granted Patent: US 8,139,395 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in a matrix shape, a first voltage applying circuit for applying a writing voltage pulse to a first bit line, and a second voltage applying circuit for applying a pre-charge voltage to a first and second bit line, such that at the time of the writing of a memory cell, the first voltage applying circuit pre-charges the two ends of the memory cell to the same voltage in advance, and after that, the second voltage applying circuit applies a writing voltage pulse via the first bit line directly connected to the transistor for selection.

Claims

1. A semiconductor memory device, comprising:

a memory cell array formed of a number of memory cells aligned in a matrix shape in a row direction and a column direction, each memory cell comprising a memory element and a cell transistor, wherein the memory element has two input/output terminals so that information is stored using a difference in electrical properties between the two terminals and the stored information is written by applying a writing voltage across the two terminals, the cell transistor has two input/output terminals and one control terminal, and a first end of the input/output terminal of the memory element and a first end of the input/output terminal of the cell transistor are connected;

word lines extending in the row direction for connecting control terminals of the cell transistors in the memory cells aligned in same rows to each other;

first bit lines extending in the column direction for connecting second ends of the input/output terminals of the cell transistors in the memory cells aligned in same columns to each other, the second end being not connected to the memory elements;

second bit lines extending in the row or column direction for connecting second ends of the input/output terminals of the memory elements in the memory cells to each other, the second ends being not connected to the cell transistors;

a word line voltage applying circuit for applying a voltage to a word line connected to the memory cell selected to be written;

a first voltage applying circuit for applying the writing voltage to the first bit line connected to the selected memory cell; and

a second voltage applying circuit for applying a pre-charge voltage to both the first bit line and the second bit line connected to the selected memory cell before application of the writing voltage.

2. The semiconductor memory device according to claim 1, wherein the second bit lines extend in the column direction.

3. The semiconductor memory device according to claim 1, wherein

in the memory cell array, two adjacent rows of memory cells share one second bit line in a case where the second bit lines extend in the row direction, and two adjacent columns of memory cells share one second bit line in a case where the second bit lines extend in the column direction.

4. The semiconductor memory device according to claim 1, wherein

the second voltage applying circuit has a pre-charge power supply line to which the pre-charge voltage is applied, and

the pre-charge power supply line is directly connected to each of the second bit lines and connected to each of the first bit lines via a first transistor.

5. The semiconductor memory device according to claim 1, wherein

the first voltage applying circuit has a writing power supply line to which the writing voltage is applied, and

the writing power supply line is connected to each of the first bit lines via a second transistor.

6. The semiconductor memory device according to claim 1, wherein

the first voltage applying circuit has a first writing power supply line and a second writing power supply line to which the writing voltages different from the pre-charge voltage are applied, respectively.

7. The semiconductor memory device according to claim 6, wherein

the first writing power supply line is connected to each of the first bit lines via a third transistor, and

the second writing power supply line is connected to each of the first bit lines via a fourth transistor.

8. The semiconductor memory device according to claim 6, wherein

the pre-charge voltage is a voltage between one of the writing voltages applied to the first writing power supply line and the other one of the writing voltages applied to the second writing power supply line.

9. The semiconductor memory device according to claim 2, wherein

the second voltage applying circuit has a pre-charge power supply line to which the pre-charge voltage is applied, and

the pre-charge power supply line is directly connected to each of the second bit lines and connected to each of the first bit lines via a first transistor.

10. The semiconductor memory device according to claim 2, wherein

the first voltage applying circuit has a writing power supply line to which the writing voltage is applied, and

the writing power supply line is connected to each of the first bit lines via a second transistor.

11. The semiconductor memory device according to claim 2, wherein

the first voltage applying circuit has a first writing power supply line and a second writing power supply line to which the writing voltages different from the pre-charge voltage are applied, respectively.

12. The semiconductor memory device according to claim 11, wherein

the first writing power supply line is connected to each of the first bit lines via a third transistor, and

the second writing power supply line is connected to each of the first bit lines via a fourth transistor.

13. The semiconductor memory device according to claim 11, wherein

the pre-charge voltage is a voltage between one of the writing voltages applied to the first writing power supply line and the other one of the writing voltages applied to the second writing power supply line.

14. The semiconductor memory device according to claim 1, wherein

the memory elements are variable resistive elements of which a resistance state represented by resistance properties between the two input/output terminals of the memory elements transitions through the application of the writing voltage.

15. An electronic apparatus comprising the semiconductor memory device according to claim 1.