Embedded Semiconductor Device Including Planarization Resistance Patterns and Method of Manufacturing the Same

• US 20100297820A1
• Filed: 08/04/2010
• Published: 11/25/2010
• Est. Priority Date: 08/25/2006
• Status: Active Grant

• Current Assignee: Boung-Ju Lee, Il-Young Yoon, Se-Young Lee
• Original Assignee: Boung-Ju Lee, Il-Young Yoon, Se-Young Lee
• Inventors: LEE, Boung-ju, LEE, Se-young, YOON, IL-young
• Granted Patent: US 8,263,454 B2
• Time in Patent Office: Days
• US Class Current: 438/253
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the substrate, a first interlayer dielectric (ILD) layer which covers the gates and the source/drain regions, first via plugs which vertically penetrate the first ILD layer and are selectively connected to the source/drain regions, capacitors and second via plugs selectively connected to the first via plugs, a second ILD layer that fills the space between the capacitors and the second via plugs, planarization resistance patterns formed on the second ILD layer, a third ILD layer formed on the second ILD layer and the planarization resistant patterns, and third via plugs which vertically penetrate the third ILD layer, and are selectively connected to a top electrode of the capacitors and the second via plugs.

Claims

1. A method of fabricating an MML semiconductor device, the method comprising:

forming gates on a substrate including a memory region and a logic region;

forming a source region and a drain region on respective sides of the gates in the substrate;

forming a first interlayer dielectric (ILD) layer which covers the gates;

forming first via plugs which vertically penetrate the first ILD layer, and are selectively connected to the source region and the drain region,

forming a second ILD layer on the first via plugs and the first ILD layer;

forming capacitors which vertically penetrate the second ILD layer, selectively connected to the first via plugs, and including a bottom electrode, a capacitor dielectric layer, and a top electrode, wherein the part of the top electrode and the capacitor dielectric layer are extended on the second ILD layer;

selectively forming planarization resistance patterns on the second ILD layer in the logic region while simultaneously forming the capacitors in the memory region;

forming a third ILD layer on the capacitors and the planarization resistance patterns;

entirely planarizing the third ILD layer;

forming second via plugs which vertically penetrate the third ILD layer and the second ILD layer, and are selectively connected to the first via plugs; and

forming a third via plug which vertically penetrates the third ILD layer, and is connected to the top electrode of the capacitors.

2. The method of claim 1, wherein the bottom electrode of the capacitor is formed to substantially a height of the second ILD layer;

and

the capacitor dielectric layer and the top electrode are extended on the second ILD layer.

3. The method of claim 1, wherein the capacitors are formed in the memory region, and the planarization resistance patterns are formed in the logic region.

4. The method of claim 1, wherein the planarization resistance patterns comprise a plurality of multiple layers.

5. The method of claim 4, wherein the planarization resistance patterns include an upper resistance pattern formed of a material used as the top electrode of the capacitors.

6. The method of claim 5, further comprising a capping layer of the planarization resistance patterns formed on the upper resistance pattern.

7. The method of claim 6, wherein the capping layer of the planarization resistance patterns are extended on the second ILD layer.

8. The method of claim 4, wherein the planarization resistance patterns include a lower resistance pattern formed of a material used as the capacitor dielectric layer.

9. The method of claim 1, wherein the second via plugs are separated from the planarization resistance patterns by a distance greater than a horizontal width of the second via plugs.

10. The method of claim 1, further comprising a capacitor capping layer formed on the top electrode of the capacitors.