MULTIPROCESSOR SYSTEM AND COMPUTER PROGRAM PRODUCT

• US 20100299472A1
• Filed: 11/06/2009
• Published: 11/25/2010
• Est. Priority Date: 05/25/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Hiroaki, Kodaka, Takeshi
• Granted Patent: US 8,145,820 B2
• Time in Patent Office: Days
• US Class Current: 710/269
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a multiprocessor system including a plurality of processors, the processors execute, at a time of migration a task operating in own processor to another processor, a transmitting task for transmitting the migration target task to a destination processor, and when an interrupt request to be received and executed by an interrupt handler accompanying the migration target task is generated during transmission of the migration target task, the transmitting task receives the interrupt request instead of the interrupt handler and starts the interrupt handler.

Claims

1. A multiprocessor system comprising a plurality of processors, wherein

the processors execute, at a time of migrating a task running on own processor to another processor, a transmitting task for transmitting the migration target task to a destination processor, and

when an interrupt request to be received and handled by an interrupt handler accompanying the migration target task is generated during transmission of the migration target task, the transmitting task receives the interrupt request instead of the interrupt handler and starts the interrupt handler.

2. The multiprocessor system according to claim 1, further comprising a storage unit that is readable and writable by the processors, wherein

the transmitting task transmits the migration target task to the destination processor via the storage unit.

3. The multiprocessor system according to claim 1, wherein

the destination processor executes a receiving task for receiving the migration target task,

the receiving task gets an interrupt handle permission to perform an interrupt handler accompanying the migration target task, which is got by only one of the own processor and a source processor of the migration target task, and after completion of reception of the migration target task by the own processor, deletes the migration target task from the source processor and gets out the interrupt handle permission, and

upon reception of the interrupt request, a transmitting task being executed by the source processor attempts to get the interrupt handle permission, and when the interrupt handle permission is got, starts an interrupt handler accompanying the migration target task.

4. The multiprocessor system according to claim 3, further comprising a storage unit that is readable and writable by the processors, wherein

the storage unit stores interrupt handle permission information that indicates a processor that has the interrupt handle permission, among the processors.

5. The multiprocessor system according to claim 1, wherein

the processors includes a processor that executes a migration instruction task for generating migration control information in which a migration target task and a destination processor of the migration target task are specified, and

a transmitting task being executed by a source processor of the migration target task transmits the migration target task based on the migration control information.

6. The multiprocessor system according to claim 5, further comprising a storage unit that is readable and writable by the processors, wherein

the storage unit stores the migration control information.

7. The multiprocessor system according to claim 5, wherein when there is a processor that is executing tasks of a number exceeding a predetermined number, the task operating in the processor is specified as a migration target task, and a processor, in which number of tasks being executed does not exceed the predetermined number even if the migration target task is added thereto, is specified as a destination processor.

8. The multiprocessor system according to claim 5, wherein when a total number of tasks being executed by the processors becomes a state that can be executed by fewer number of processors, the migration instruction task generates migration control information specifying all the tasks being executed by a processor having smallest number of tasks being executed as migration target tasks.

9. The multiprocessor system according to claim 7, wherein the migration instruction task causes a processor that is executing the migration target task to start the transmitting task.

10. The multiprocessor system according to claim 8, wherein the migration instruction task causes a processor that is executing the migration target task to start the transmitting task.

11. A computer program product comprising a plurality of commands executable by a computer including a plurality of processors, wherein

at a time of migrating a task running on own processor to another processor, when an interrupt request to be received and handled by an interrupt handler accompanying the migration target task occurs during transmission of the migration target task, the commands cause each of the processors to receive the interrupt request instead of the interrupt handler and start the interrupt handler.

12. The computer program product according to claim 11, wherein

the commands further cause each of the processors to:

get an interrupt handle permission to perform an interrupt handling accompanying the migration target task, which is by only one of the own processor and a source processor of the migration target task, at the time of receiving the migration target task; and

delete the migration target task from the source processor and get out the interrupt handle permission, after completion of reception of the migration target task by the own processor.

13. The computer program product according to claim 12, wherein

the commands further causes each of the processors to:

attempt to get the interrupt handle permission when the interrupt request is received during transmission of the migration target task; and

start an interrupt handler accompanying the migration target task when the interrupt handle permission is ensured.