MULTI-CORE PROCESSOR SYSTEM

• US 20100299541A1
• Filed: 11/02/2009
• Published: 11/25/2010
• Est. Priority Date: 05/21/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kizu, Toshiki, Ishikawa, Yuji, Ohyama, Ryuichiro
• Granted Patent: US 8,214,679 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-core processor system includes: a plurality of processor cores; a power supply unit that stops supplying or supplies power to each of the processor cores individually; and a thread queue that stores threads that the multi-core processor system causes the processor cores to execute. Each of the processor cores includes: a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a number of threads stored in the thread queue is equal to or smaller than a first threshold; and a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the number of threads stored in the thread queue exceeds a second value equal to or lager than the first threshold.

Claims

1. A multi-core processor system comprising:

a plurality of processor cores;

a power supply unit that stops supplying or supplies power to each of the processor cores individually; and

a thread queue that stores threads that the multi-core processor system causes the processor cores to execute, wherein

each of the processor cores includes;

a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a number of threads stored in the thread queue is equal to or smaller than a first threshold; and

a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the number of threads stored in the thread queue exceeds a second value equal to or lager than the first threshold.

2. The multi-core processor system according to claim 1, further comprising a storing unit that stores the thread queue.

3. The multi-core processor system according to claim 2, wherein both the first threshold and the second threshold are zero.

4. The multi-core processor system according to claim 2, further comprising:

a timer; and

a power-off time table in which power-off time of each of the processor core is recorded, wherein

the power-supply stopping unit acquires time referring to the timer before stopping the power supply to the own processor core and records the acquired time in the power-off time table as power-off time, and

the power-supply resuming unit resumes, when the number of threads stored in the thread queue exceeds the second threshold, power supply to a processor core in which a predetermined time has elapsed from the power-off time recorded in the power-off time table among the stopped processor cores.

5. The multi-core processor system according to claim 4, wherein the storing unit stores the power-off time table.

6. The multi-core processor system according to claim 2, wherein the second threshold is a value lager than the first threshold.

7. The multi-core processor system according to claim 2, wherein the first threshold and the second threshold increase or decrease according to an increase or decrease of a number of processor cores that are executing threads.

8. A multi-core processor system comprising:

a plurality of processor cores;

a power supply unit that stops supplying or supplies power to each of the processor cores individually; and

a thread queue that stores threads that the multi-core processor system causes the processor cores to execute, wherein

each of the processor cores includes;

a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a resource of an own processor core satisfies none of resource requests of threads stored in the thread queue; and

a power-supply resuming unit that causes, when there is a processor core having a resource that satisfies the resource requests of the threads stored in the thread queue among the other stopped processor cores the power supply unit to resume power supply to the other processor core.

9. The multi-core processor system according to claim 8, further comprising a storing unit that stores the thread queue.

10. The multi-core processor system according to claim 9, wherein the storing unit stores a plurality of thread queues for each of resource requests of threads stored therein.

11. The multi-core processor system according to claim 10, wherein the storing unit stores a requested resource list in which a requested resource for each of the thread queues is described and a processor-core resource list in which a resource for each of the processor cores is described.

12. The multi-core processor system according to claim 9, wherein

the thread queue stores, for each of threads, a resource request of a thread stored therein, and

the storing unit stores a processor-core resource list in which a resource for each of the processor cores is described.

13. A multi-core processor system comprising:

a plurality of processor cores;

a power supply unit that stops supplying or supplies power to each of the processor cores individually;

a timer;

a thread queue that stores, together with calculation time information indicating time necessary for execution, threads that the multi-core processor system causes the processor cores to execute; and

a thread-end-predicted time table that records end-predicted time of a thread being executed by each of the processor cores, wherein

each of the processor cores includes;

an end-predicted-time recording unit that calculates, when a thread is acquired from the thread queue, end-predicted time of the acquired thread based on the calculation time information stored in the thread queue and a value of the timer and writes the calculated end-predicted time in the thread-end-predicted time table;

a power-supply stopping unit calculates, based on the thread-end-predicted time table and the value of the timer, a number of end-expected cores as a number of processor cores that are expected to end thread execution soon and causes the power supply unit to stop power supply to an own processor core when a value obtained by subtracting the calculated number of end-expected cores from a number of threads stored in the thread queue is equal to or smaller than a first threshold; and

a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the value obtained by subtracting the calculated number of end-expected cores from the number of threads stored in the thread queue exceeds a second threshold equal to or larger than the first threshold.

14. The multi-core processor system according to claim 13, further comprising a storing unit that stores the thread queue and the thread-end-predicted time table.