SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20100301329A1
• Filed: 05/26/2010
• Published: 12/02/2010
• Est. Priority Date: 05/29/2009
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KOEZUKA, Junichi, ASANO, Yuji
• Application Number:
  US12/787,813
• Publication Number:
  US 20100301329A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. Another object is to provide a method for manufacturing the thin film transistor. A thin film transistor using an oxide semiconductor layer is formed in such a manner that buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, source and drain electrode layers are formed over the buffer layers, and the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween. In addition, the buffer layers are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer are obtained.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a first buffer layer and a second buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the first buffer layer and the second buffer layer,

wherein the first buffer layer and the second buffer layer have higher conductivity than the oxide semiconductor layer and are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, and

the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the first buffer layer and the second buffer layer interposed therebetween.

5. The semiconductor device according to claim 1, wherein the first buffer layer and the second buffer layer are formed using a non-single-crystal film formed from an oxide semiconductor.

7. The semiconductor device according to claim 1, wherein the first buffer layer and the second buffer layer are formed using a non-single-crystal film formed from an oxide semiconductor including nitrogen.

9. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is formed through heat treatment in a nitrogen atmosphere.

11. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is formed through heat treatment in an air atmosphere.

13. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a region which is located between the first buffer layer and the second buffer layer and whose thickness is smaller than that of a region overlapping with the first buffer layer and the second buffer layer.

15. The semiconductor device according to claim 1, wherein a width in a channel direction of the gate electrode layer is smaller than a width in the channel direction of the oxide semiconductor layer.

2. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a high-conductive oxide semiconductor layer over the gate insulating layer;

an oxide semiconductor layer over the high-conductive oxide semiconductor layer;

a first buffer layer and a second buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the first buffer layer and the second buffer layer,

wherein the first buffer layer and the second buffer layer have higher conductivity than the oxide semiconductor layer and are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere,

the high-conductive oxide semiconductor layer has higher conductivity than the oxide semiconductor layer and is subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, and

the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the first buffer layer and the second buffer layer interposed therebetween.

3. The semiconductor device according to claim 2, wherein the high-conductive oxide semiconductor layer is formed using a non-single-crystal film formed from an oxide semiconductor.

4. The semiconductor device according to claim 2, wherein the high-conductive oxide semiconductor layer is formed using a non-single-crystal film formed from an oxide semiconductor including nitrogen.

6. The semiconductor device according to claim 2, wherein the first buffer layer and the second buffer layer are formed using a non-single-crystal film formed from an oxide semiconductor.

8. The semiconductor device according to claim 2, wherein the first buffer layer and the second buffer layer are formed using a non-single-crystal film formed from an oxide semiconductor including nitrogen.

10. The semiconductor device according to claim 2, wherein the oxide semiconductor layer is formed through heat treatment in a nitrogen atmosphere.

12. The semiconductor device according to claim 2, wherein the oxide semiconductor layer is formed through heat treatment in an air atmosphere.

14. The semiconductor device according to claim 2, wherein the oxide semiconductor layer includes a region which is located between the first buffer layer and the second buffer layer and whose thickness is smaller than that of a region overlapping with the first buffer layer and the second buffer layer.

16. The semiconductor device according to claim 2, wherein a width in a channel direction of the gate electrode layer is smaller than a width in the channel direction of the oxide semiconductor layer.

17. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor film over the gate insulating layer, using a sputtering method;

subjecting the first oxide semiconductor film to heat treatment;

forming a second oxide semiconductor film over the first oxide semiconductor film using a sputtering method;

subjecting the second oxide semiconductor film to reverse sputtering treatment;

subjecting the second oxide semiconductor film to heat treatment in a nitrogen atmosphere;

etching the first oxide semiconductor film and the second oxide semiconductor film to form an oxide semiconductor layer and a first buffer layer;

forming a conductive film over the oxide semiconductor layer and the first buffer layer;

etching the conductive film and the first buffer layer to form source and drain electrode layers, a second buffer layer, and a third buffer layer; and

subjecting the oxide semiconductor layer to heat treatment,

wherein the second buffer layer and the third buffer layer have higher conductivity than the oxide semiconductor layer.

19. The method for manufacturing a semiconductor device, according to claim 17, wherein the first oxide semiconductor film is subjected to heat treatment in a nitrogen atmosphere.

21. The method for manufacturing a semiconductor device, according to claim 17, wherein the first oxide semiconductor film is subjected to heat treatment in an air atmosphere.

23. The method for manufacturing a semiconductor device, according to claim 17, wherein the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere.

25. The method for manufacturing a semiconductor device, according to claim 17, wherein the oxide semiconductor layer is subjected to heat treatment in an air atmosphere.

27. The method for manufacturing a semiconductor device, according to claim 17, wherein the heat treatment of the first oxide semiconductor film is performed at 250°

C. to 500°

C. inclusive.

29. The method for manufacturing a semiconductor device, according to claim 17, wherein the heat treatment of the second oxide semiconductor film in a nitrogen atmosphere is performed at 250°

C. to 500°

C. inclusive.

31. The method for manufacturing a semiconductor device, according to claim 17, wherein the heat treatment of the oxide semiconductor layer is performed at 250°

C. to 500°

C. inclusive.

33. The method for manufacturing a semiconductor device, according to claim 17, wherein the second oxide semiconductor film is formed in an atmosphere of a rare gas and a nitrogen gas.

18. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor film over the gate insulating layer using a sputtering method;

subjecting the first oxide semiconductor film to heat treatment;

forming a second oxide semiconductor film over the first oxide semiconductor film using a sputtering method;

subjecting the second oxide semiconductor film to heat treatment in a nitrogen atmosphere;

subjecting the second oxide semiconductor film to reverse sputtering treatment;

etching the first oxide semiconductor film and the second oxide semiconductor film to form an oxide semiconductor layer and a first buffer layer;

forming a conductive film over the oxide semiconductor layer and the first buffer layer;

etching the conductive film and the first buffer layer to form source and drain electrode layers, a second buffer layer, and a third buffer layer; and

subjecting the oxide semiconductor layer to heat treatment,

wherein the second buffer layer and the third buffer layer have higher conductivity than the oxide semiconductor layer.

20. The method for manufacturing a semiconductor device, according to claim 18, wherein the first oxide semiconductor film is subjected to heat treatment in a nitrogen atmosphere.

22. The method for manufacturing a semiconductor device, according to claim 18, wherein the first oxide semiconductor film is subjected to heat treatment in an air atmosphere.

24. The method for manufacturing a semiconductor device, according to claim 18, wherein the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere.

26. The method for manufacturing a semiconductor device, according to claim 18, wherein the oxide semiconductor layer is subjected to heat treatment in an air atmosphere.

28. The method for manufacturing a semiconductor device, according to claim 18, wherein the heat treatment of the first oxide semiconductor film is performed at 250°

C. to 500°

C. inclusive.

30. The method for manufacturing a semiconductor device, according to claim 18, wherein the heat treatment of the second oxide semiconductor film in a nitrogen atmosphere is performed at 250°

C. to 500°

C. inclusive.

32. The method for manufacturing a semiconductor device, according to claim 18, wherein the heat treatment of the oxide semiconductor layer is performed at 250°

C. to 500°

C. inclusive.

34. The method for manufacturing a semiconductor device, according to claim 18, wherein the second oxide semiconductor film is formed in an atmosphere of a rare gas and a nitrogen gas.