Detecting a Fault State of a Semiconductor Arrangement

• US 20100301332A1
• Filed: 05/29/2009
• Published: 12/02/2010
• Est. Priority Date: 05/29/2009
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Barrenscheen, Jens, Dibra, Donald
• Application Number:
  US12/474,959
• Publication Number:
  US 20100301332A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01K 1/026 arrangements for monitoring a plurality of temperatures, e.g. by multiplexing
• CPC Class Codes: G01K 2213/00 Temperature mapping
• CPC Class Codes: G01K 7/42 Circuits effecting compensation of thermal inertia; Circuits for predicting the stationary value of a temperature
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Disclosed is a method for detecting a mechanical fault state of a semiconductor arrangement, using a temperature profile.

Claims

1. A method for detecting a mechanical fault state of a semiconductor arrangement, the method comprising:

obtaining a temperature profile that includes n temperatures, with n≧

2, by determining a temperature with a temperature sensor at n different positions of the semiconductor arrangement;

evaluating the temperature profile by evaluating a relationship of at least two of the n temperatures of the temperature profile; and

detecting the presence of the fault state dependent on the result of evaluating the temperature profile.

2. The method of claim 1, wherein obtaining the temperature profile comprises:

determining the temperatures at positions of a first group of positions, the first group including at least one position, and determining the temperatures at positions of a second group of positions, the second group including at least one position, the temperatures at the positions of the first group being different from the temperatures at the positions of the second group in a normal state.

3. The method of claim 2, wherein the semiconductor arrangement includes at least one thermal contact and wherein the first group of positions are located closer to the at least one thermal contact than the second group of positions.

4. The method of claim 3, wherein the at least one thermal contact is also an electrical contact.

5. The method of claim 4, wherein the electrical contact comprises a bond wire contact.

6. The method of claim 3, wherein evaluating the temperature profile comprises evaluating the temperatures of one position of the first group of positions and one position of the second group of positions.

7. The method of claim 6, wherein the presence of the fault state is detected, if a difference between the temperatures of the one position of the second group and the one position of the first group is less than a given reference value.

8. The method of claim 7, wherein the reference value is dependent on the temperature of at least one of the temperatures of the one position of the second group and the one position of the first group.

9. The method of claim 6, wherein the presence of the fault state is detected, if both of the temperatures of the two positions are above a threshold value.

10. The method of claim 9, wherein the threshold value is dependent on the temperature of at least one of the temperatures of the one position of the second group and the one position of the first group.

11. The method of claim 2,

wherein the second group of positions includes two or more positions;

wherein evaluating the temperature profile comprises calculating a mean value of the temperatures of the first group of positions; and

wherein the presence of the fault state is detected if a difference between a mean value and a temperature of one position of the first group of positions is less than a given reference value.

12. The method of claim 1, wherein obtaining the temperature profile comprises:

determining temperatures at positions of a group of positions, the group including at least two positions, the temperatures at the positions of this group being within a given temperature range in a normal state.

13. The method of claim 12, wherein the presence of the fault state is detected, if one of the temperatures is outside the given temperature range.

14. The method of claim 13, wherein the given temperature range is dependent on a mean value of the temperatures.

15. The method of claim 12, wherein the temperature sensor includes at least two sensors and the semiconductor arrangement includes at least two thermal contacts and wherein the sensors are located near of the at least two thermal contacts.

16. The method of claim 15, wherein the thermal contacts are also electrical contacts.

17. The method of claim 16, wherein the electrical contacts comprise bond wire contacts.

18. The method of claim 12,

wherein the semiconductor arrangement comprises a carrier and a semiconductor body mounted to the carrier, and

wherein the positions are located in the vicinity of an interface between the semiconductor body and the carrier.

19. The method according to claim 1, wherein the semiconductor arrangement comprises a power semiconductor device.

20. The method according to claim 1, wherein the semiconductor arrangement comprises an integrated circuit.

21. A semiconductor arrangement comprising:

n temperature sensors, with n≧

2, that are located at n different positions of the semiconductor arrangement and that provide temperature signals; and

an evaluation circuit coupled to the temperature sensors, the evaluation circuit being adapted to evaluate a relationship of at least two of the n temperatures of a temperature profile, the evaluation circuit providing a state signal that indicates one of a normal state or a mechanical fault state dependent on a result of evaluating the temperature profile.

22. The semiconductor arrangement of claim 21, wherein the temperature sensors comprise a first group of temperature sensors, the first group including at least one temperature sensor, and a second group of temperature sensors, the second group including at least one position, locations of positions of the first and second group of temperature sensors being such that temperatures at the positions of the first group are different from temperatures at the positions of the second group in the normal state.

23. The semiconductor arrangement of claim 22, further comprising at least one thermal contact, the positions of the first group of temperature sensors being located closer to the at least one thermal contact than the positions of the second group of temperature sensors.

24. The semiconductor arrangement of claim 21, wherein the temperature sensors are located such that temperatures at the positions are within a given temperature range in the normal state.

25. The semiconductor arrangement of claim 24, wherein the semiconductor arrangement includes at least two thermal contacts and wherein the temperature sensors are located in the vicinity of the at least two thermal contacts.