HIGH VOLTAGE SWITCHING DEVICES AND PROCESS FOR FORMING SAME

• US 20100301351A1
• Filed: 08/06/2010
• Published: 12/02/2010
• Est. Priority Date: 04/30/2002
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Brandes, George R., Vaudo, Robert P., Flynn, Jeffrey S.
• Granted Patent: US 8,174,089 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm⁻³) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).

Claims

1. A microelectronic device structure, comprising:

(a) a foreign substrate;

(b) a nucleation buffer layer overlying said foreign substrate;

(c) a first GaN layer overlying said nucleation buffer layer, said first GaN layer having a dopant concentration of not more than about 1×

10¹⁶/cm³;

(d) a second, conductive GaN layer overlying said first GaN layer;

(e) a third GaN layer overlying said second, conductive GaN layer, said third GaN layer having a dopant concentration of not more than about 1×

10¹⁶/cm³; and

(f) at least one metal contact over said third GaN layer, forming a metal-to-semiconductor junction therewith.

2. The microelectronic device structure of claim 1, wherein said foreign substrate comprises a material selected from the group consisting of sapphire, Si, and SiC.

3. The microelectronic device structure of claim 1, wherein said foreign substrate comprises sapphire.

4. The microelectronic device structure of claim 1, wherein the third GaN layer is less than 10 μ

m in thickness.

5. The microelectronic device structure of claim 1, wherein the third GaN layer is less than 20 μ

m in thickness.

6. The microelectronic device structure of claim 1, wherein the third GaN layer is less than 50 μ

m in thickness.

7. The microelectronic device structure of claim 1, wherein the second, conductive GaN layer is doped with a strain-reducing dopant.

8. The microelectronic device structure of claim 1, wherein the second, conductive GaN layer is doped with germanium.

9. The microelectronic device structure of claim 1, wherein the first GaN layer has a thickness of about 0.6 μ

m, wherein the second, conductive GaN layer has a thickness of about 2.0 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein the third GaN layer has a thickness of at least about 2.5 μ

m.

10. The microelectronic device structure of claim 1, wherein the first GaN layer has a thickness of about 0.6 μ

m, wherein the second, conductive GaN layer has a thickness of about 0.5 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein the third GaN layer has a thickness of at least about 2.5 μ

m.

11. The microelectronic device structure of claim 1, wherein said second, conductive GaN layer comprises a first conductive GaN sub-layer of a first dopant concentration and a second conductive GaN sub-layer of a second dopant concentration, wherein said first conductive GaN sub-layer is adjacent to the first GaN layer, wherein said second conductive GaN sub-layer is adjacent to said third GaN layer, and wherein said first dopant concentration is lower than said second dopant concentration.

12. The microelectronic device structure of claim 11, wherein said first GaN layer has a thickness of about 0.6 μ

m, wherein said first conductive GaN sub-layer has a thickness of about 1.9 μ

m and a dopant concentration of about 2.0×

10¹⁸/cm³, wherein said second conductive GaN sub-layer has a thickness of about 0.1 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein said third GaN layer has a thickness of at least about 2.5 μ

m.

13. A microelectronic device structure, comprising:

(a) a foreign substrate;

(b) a nucleation buffer layer overlying said foreign substrate;

(c) a first GaN layer overlying said nucleation buffer layer, said first GaN layer having a dopant concentration of not more than about 1×

10¹⁶/cm³;

(d) a second GaN layer of n-type conductivity, overlying said first GaN layer;

(e) a third GaN layer overlying said second GaN layer of n-type conductivity, said third GaN layer having a dopant concentration of not more than about 1×

10¹⁶/cm³; and

(f) a fourth GaN layer of p-type conductivity, formed over said third GaN layer; and

(g) at least one metal contact overlying said fourth GaN layer.

14. The microelectronic device structure of claim 13, wherein said foreign substrate comprises a material selected from the group consisting of sapphire, Si, and SiC.

15. The microelectronic device structure of claim 13, wherein said foreign substrate comprises sapphire.

16. The microelectronic device structure of claim 13, wherein the third GaN layer is less than 10 μ

m in thickness.

17. The microelectronic device structure of claim 13, wherein the third GaN layer is less than 20 μ

m in thickness.

18. The microelectronic device structure of claim 13, wherein the third GaN layer is less than 50 μ

m in thickness.

19. The microelectronic device structure of claim 13, wherein the second GaN layer of n-type conductivity is doped with a strain-reducing dopant.

20. The microelectronic device structure of claim 13, wherein the second GaN layer of n-type conductivity is doped with germanium.

21. The microelectronic device structure of claim 13, wherein the first GaN layer has a thickness of about 0.6 μ

m, wherein the second GaN layer of n-type conductivity has a thickness of about 2.0 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein the third GaN layer has a thickness of at least about 2.5 μ

m.

22. The microelectronic device structure of claim 13, wherein the first GaN layer has a thickness of about 0.6 μ

m, wherein the second GaN layer of n-type conductivity has a thickness of about 0.5 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein the third GaN layer has a thickness of at least about 2.5 μ

m.

23. The microelectronic device structure of claim 13, wherein said second GaN layer of n-type conductivity comprises a first conductive GaN sub-layer of a first dopant concentration and a second conductive GaN sub-layer of a second dopant concentration, wherein said first conductive GaN sub-layer is adjacent to the first GaN layer, wherein said second conductive GaN sub-layer is adjacent to said third GaN layer, and wherein said first dopant concentration is lower than said second dopant concentration.

24. The microelectronic device structure of claim 23, wherein said first GaN layer has a thickness of about 0.6 μ

m, wherein said first conductive GaN sub-layer has a thickness of about 1.9 μ

m and a dopant concentration of about 2.0×

10¹⁸/cm³, wherein said second conductive GaN sub-layer has a thickness of about 0.1 μ

m and a dopant concentration of about 1.5×

10¹⁹/cm³, and wherein said third GaN layer has a thickness of at least about 2.5 μ

m.

25. A microelectronic device structure adapted for high voltage operation, said microelectronic device structure comprising:

(a) a first conductive GaN base layer comprising a GaN structure having a thickness of greater than about 50 μ

m and having a top surface characterized by a dislocation defect density of not more than about 5×

10⁶/cm²;

(b) a second GaN layer having a dopant concentration of not more than about 1×

10¹⁶/cm³, disposed adjacent to the top surface of said first conductive GaN base layer; and

(c) at least one metal contact adjacent to at least one of (i) the top surface of said first conductive GaN base layer and (ii) said second GaN layer, forming a metal-to-semiconductor junction with at least one of said first conductive GaN base layer and said second GaN layer;

wherein said microelectronic device structure has a breakdown voltage of at least about 450V.

26. The microelectronic device structure of claim 25, having a breakdown voltage of at least 1000V.

27. The microelectronic device structure of claim 25, having a breakdown voltage of at least 2000V.

28. A microelectronic device structure adapted for high voltage operation, said microelectronic device structure comprising:

(a) a first GaN layer of n-type conductivity and comprising a GaN structure having a thickness of greater than about 50 μ

m and having a top surface characterized by a dislocation defect density of not more than about 5×

10⁶/cm²;

(b) a second GaN layer having a dopant concentration of not more than about 1×

10¹⁵/cm³, disposed adjacent to said first GaN layer;

(c) a third GaN layer of p-type conductivity, disposed adjacent to said second GaN layer; and

(d) at least one metal contact disposed adjacent to said third GaN layer;

wherein the microelectronic device structure has a breakdown voltage of at least about 450V.

29. The microelectronic device structure of claim 28, having a breakdown voltage of at least 1000V.

30. The microelectronic device structure of claim 28, having a breakdown voltage of at least 2000V.