ELECTROSTATIC DISCHARGE PROTECTION DEVICE

• US 20100301385A1
• Filed: 05/26/2009
• Published: 12/02/2010
• Est. Priority Date: 05/26/2009
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Tsai, Hung-Shern, Tu, Shang-Hui
• Granted Patent: US 8,008,687 B2
• Time in Patent Office: Days
• US Class Current: 257/137
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Abstract

An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region.

Claims

1. An electrostatic discharge protection device, comprising:

a substrate having a first conductive type;

a first doped region having a second conductive type and formed in the substrate;

a first gate electrode formed on the substrate;

a second doped region having the second conductive type and formed in the substrate, wherein a transistor is constituted by the first doped region, the first gate electrode, and the second doped region;

a second gate electrode formed on the substrate, wherein the first and the second gate electrodes are separated; and

a third doped region having the first conductive type and formed in the substrate, wherein a discharge element is constituted by the first doped region, the second gate electrode, and the third doped region.

2. The electrostatic discharge protection device as claimed in claim 1, further comprising a fourth doped region having the first conductive type and formed in the substrate for isolating the second and the third doped regions.

3. The electrostatic discharge protection device as claimed in claim 2, wherein the fourth doped region further isolates the first and the second gate electrodes.

4. The electrostatic discharge protection device as claimed in claim 1, wherein the transistor is a laterally diffused metal oxide semiconductor field effect transistor (LDMOS FET) and the discharge element is an insulated gate bipolar transistor (IGBT).

5. The electrostatic discharge protection device as claimed in claim 4, wherein the first doped region serves as a source of the transistor and the second doped region serves as a drain of the transistor.

6. The electrostatic discharge protection device as claimed in claim 5, wherein the first doped region serves as a source of the discharge element and the third doped region serves as a drain of the discharge element.

7. The electrostatic discharge protection device as claimed in claim 1, further comprising a metal layer electrically connecting the second gate electrode and the first doped region.

8. The electrostatic discharge protection device as claimed in claim 1, further comprising an input/output pad formed on the second doped region.

9. The electrostatic discharge protection device as claimed in claim 1, further comprising:

a first field oxide formed between the first gate electrode and the second doped region; and

a second field oxide formed between the second gate electrode and the third doped region.

10. The electrostatic discharge protection device as claimed in claim 9, wherein the width of the second field oxide is narrower than or equal to the width of the first field oxide.

11. The electrostatic discharge protection device as claimed in claim 9, wherein the first and the second field oxides are separated.

12. The electrostatic discharge protection device as claimed in claim 1, wherein the first conductive type is a P type and the second conductive type is an N type.

13. An electrostatic discharge protection device, comprising:

a substrate having a first conductive type;

a first doped region having a second conductive type and formed in the substrate;

a first gate electrode formed on the substrate;

a second doped region having the second conductive type and formed in the substrate, wherein a transistor is constituted by the first doped region, the first gate electrode, and the second doped region;

a third doped region having the first conductive type and formed in the substrate, wherein the second and the third doped regions are separated; and

a fourth doped region having the second conductive type and formed in the substrate, wherein the second and the fourth doped regions are separated, and a discharge element is constituted by the first, the third, and the fourth doped regions and the second gate electrode.

14. The electrostatic discharge protection device as claimed in claim 13, further comprising a fifth doped region having the first conductive type and formed in the substrate for isolating the second doped region from the third and the fourth doped regions.

15. The electrostatic discharge protection device as claimed in claim 13, wherein the transistor is a laterally diffused metal oxide semiconductor field effect transistor (LDMOS FET) and the discharge element is a silicon controlled rectifier (SCR).

16. The electrostatic discharge protection device as claimed in claim 15, wherein the first doped region serves as a source of the transistor and the second doped region serves as a drain of the transistor.

17. The electrostatic discharge protection device as claimed in claim 15, wherein the first doped region serves as a source of the discharge element and the third and the fourth doped regions are served as a drain of the discharge element.

18. The electrostatic discharge protection device as claimed in claim 13, further comprising a metal layer electrically connecting to the second gate electrode and the first doped region.

19. The electrostatic discharge protection device as claimed in claim 13, further comprising an input/output pad formed on the second doped region.

20. The electrostatic discharge protection device as claimed in claim 13, further comprising:

a first field oxide formed between the first gate electrode and the second doped region; and

a second field oxide formed between the second gate electrode and the fourth doped region.

21. The electrostatic discharge protection device as claimed in claim 20, wherein the width of the second field oxide is narrower than or equal to the width of the first field oxide.

22. The electrostatic discharge protection device as claimed in claim 20, wherein the first and the second field oxide are separated.

23. The electrostatic discharge protection device as claimed in claim 13, further comprising a metal layer electrically connecting to the third and the fourth doped regions.

24. The electrostatic discharge protection device as claimed in claim 13, wherein the first conductive type is a P type and the second conductive type is an N type.