LATTICE MATCHED MULTI-JUNCTION PHOTOVOLTAIC AND OPTOELECTRONIC DEVICES

• US 20100301454A1
• Filed: 11/10/2008
• Published: 12/02/2010
• Est. Priority Date: 11/20/2007
• Status: Abandoned Application

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Yu, Shui-Qing, Johnson, Shade R., Ding, Ding, Wu, Songnan, Zhang, Yong-Hang
• Application Number:
  US12/743,113
• Publication Number:
  US 20100301454A1
• Time in Patent Office: Days
• US Class Current: 257/614
• CPC Class Codes: H01L 31/0687 Multiple junction or tandem solar cells
• CPC Class Codes: Y02B 10/10 Photovoltaic [PV]
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials

Abstract

The present invention provides semiconductor structures comprising a substrate and at least three III-V and/or II-VI multi junction building blocks, each comprising a p-n junction having at least two alloy layers, formed over the substrate, provided at least one multi-junction building block comprises II-VI alloy layers. Further described are methods for preparing semiconductor structures utilizing a sacrificial or etch-stop ternary III-V alloy layer over an III-V substrate.

Claims

1. A semiconductor structure comprising a substrate and at least two multi-junction building blocks formed over the substrate, wherein

the substrate is a III-V substrate or a II-VI substrate;

and

each multi junction building block independently comprises a p-n junction having at least two alloy layers, wherein the alloy layers are independently III-V or II-VI alloy layers, wherein one alloy layer is p-doped and the other alloy layer is n-doped,

provided at least one multi junction building block comprises II-VI alloy layers.

2. The structure of claim 1, wherein the III-V substrate comprises GaSb, InAs, or InP.

4. The structure of claim 1, wherein the II-VI substrate comprises CdSe, CdTe, or ZnTe.

5. The structure of claim 1, wherein the multi-junction building blocks are lattice matched or pseudomorphically strained to the substrate.

6. The structure of claim 1, wherein each multi junction building block further comprises a third layer of the same or different alloy as the p-n junction, and the third layer is p⁺, P, n⁺, or N doped.

11. The structure of claim 1, wherein each III-V alloy layer independently comprises a binary, ternary, or quaternary (InGaAl)(AsSbP) alloy.

13. The structure of claim 1, wherein each II-VI alloy layer independently comprise a binary, ternary, or quaternary (ZnCdHgBeMg)(SeTe) alloy.

22. The structure of claim 1, further comprising at least one tunnel junction.

24. The structure of claim 1, further comprising a buffer layer between the substrate and the first multi-junction building block foamed over the substrate.

25. The structure of claim 1, wherein each of multi junction building blocks has a bandgap greater than the multi-junction building block it is formed over.

26. The structure of claim 1, wherein each of multi junction building blocks has a bandgap less than the multi junction building block it is formed over.

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27. A method for preparing a semiconductor structure comprising,

preparing an etch-stop ternary III-V alloy layer over an III-V substrate;

preparing at least two multi junction building blocks over the etch-stop layer, wherein each multi junction building block independently comprises a p-n junction having at least two alloy layers, wherein the alloy layers are independently III-V or II-VI alloy layers, wherein one alloy layer is p-doped and the other alloy layer is n-doped, provided at least one multi junction building block comprises II-VI alloy layers;

removing the substrate; and

removing the etch-stop alloy layer.

28. The method of claim 27, wherein the III-V substrate comprises GaSb, InAs, or InP.

34. The method of claim 27, wherein each multi junction building block further comprises a third layer of the same or different alloy as the p-n junction, and the third layer is p⁺, P, n⁺, or N doped.

39. The method of claim 27, wherein each III-V alloy layer independently comprises a binary, ternary, or quaternary (InGaAl)(AsSbP) alloy.

41. The method of claim 27, wherein each II-VI alloy layer independently comprises a binary, ternary, or quaternary (ZnCdHgBeMg)(SeTe) alloy.

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55. A semiconductor structure comprising at least two multi junction building blocks, wherein

each multi junction building block independently comprises a p-n junction having at least two alloy layers, wherein the alloy layers are independently III-V or II-VI alloy layers, wherein one alloy layer is p-doped and the other alloy layer is n-doped,

provided at least one multi junction building block comprises II-VI alloy layers.

56. The structure of claim 55, wherein each multi-junction building block further comprises a third layer of the same or different alloy as the p-n junction, and the third layer is p⁺, P, n⁺, or N doped.

58. The structure of claim 55, wherein each of the multi junction building blocks is lattice matched or pseudomorphically strained to the substrate.

62. The structure of claim 55, wherein each III-V alloy layer independently comprises a binary, ternary, or quaternary (InGaAl)(AsSbP) alloy.

64. The structure of claim 55, wherein each II-VI alloy layer independently comprises a binary, ternary, or quaternary (ZnCdHgBeMg)(SeTe) alloy.

66. The structure of claim 55, wherein the bandgap of each of the multi junction building block is 0.50-3.00 eV.

73. The structure of claim 55, further comprising at least one tunnel junction.

75. The structure of claim 55, wherein each of multi junction building blocks has a bandgap greater than the multi junction building block it is formed over.

76. The structure of claim 55, wherein each of multi junction building blocks has a bandgap less than the multi junction building block it is formed over.

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77. (A method for preparing a semiconductor structure comprising

forming at least two multi junction building blocks over a substrate, wherein

the substrate is a III-V substrate or a II-VI substrate;

and

each multi junction building block independently comprises a p-n junction having at least two alloy layers, wherein the alloy layers are independently III-V or II-VI alloy layers, wherein one alloy layer is p-doped and the other alloy layer is n-doped,

provided at least one multi junction building block comprises II-VI alloy layers.

79. The method of claim 77, wherein the III-V substrate comprises GaSb, InAs, or InP.

81. The method of claim 77, wherein the II-VI substrate comprises CdSe, CdTe, or ZnTe.

83. The method of claim 77, wherein each multi-junction building block further comprises a third layer of the same or different alloy as the p-n junction, and the third layer is p⁺, P, n⁺, or N doped.

88. The method of claim 77, wherein each III-V alloy layer independently comprises a binary, ternary, or quaternary (InGaAl)(AsSbP) alloy.

90. The method of claim 77, wherein each II-VI alloy layer independently comprise a binary, ternary, or quaternary (ZnCdHgBeMg)(SeTe) alloy.

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