METHOD OF STIFFENING CORELESS PACKAGE SUBSTRATE

• US 20100301492A1
• Filed: 08/16/2010
• Published: 12/02/2010
• Est. Priority Date: 02/19/2009
• Status: Active Grant

• Current Assignee: John S. Guzek, Nicholas R. Watts, Sriram Muthukumar
• Original Assignee: John S. Guzek, Nicholas R. Watts, Sriram Muthukumar
• Inventors: Muthukumar, Sriram, Guzek, John S., Watts, Nicholas R.
• Granted Patent: US 8,860,205 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 2203/0582 Coating by resist, i.e. resist used as mask for application of insulating coating or of second resist
• CPC Class Codes: H05K 3/28 Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673
• CPC Class Codes: H05K 3/4682 Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

Claims

1. A semiconductor substrate, comprising:

a coreless substrate having a first level interconnect side adapted to chip-to-package interconnection and a second level interconnect side adapted to package-to-board interconnection; and

a molded stiffener formed on the second level interconnect side, the molded stiffener having a plurality of cavities corresponding to a plurality of contact pads, each contact pad being adapted to receive an electrically conductive interconnect.

2. The semiconductor substrate of claim 1, further comprising an electrically conductive surface finish plated on the surface of the contact pads and the sidewalls of the cavities.

3. The semiconductor substrate of claim 2, wherein the cavities have a tapering profile.