LOW NOISE, LOW POWER SUBSAMPLING RECEIVER

• US 20100301928A1
• Filed: 05/28/2010
• Published: 12/02/2010
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: Stanford University
• Original Assignee: Stanford University
• Inventors: Barth, Carsten, Linscott, Ivan Richard, Inan, Umran S.
• Granted Patent: US 8,452,252 B2
• Time in Patent Office: Days
• US Class Current: 327/557
• CPC Class Codes: H04B 1/0028 wherein the AD/DA conversion occurs at baseband stage
• CPC Class Codes: H04B 1/18 Input circuits, e.g. for coupling to an antenna or a transmission line coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H

Abstract

Techniques for a receiver includes a low noise amplifier, a Q-enhanced bandpass filter on a chip, and an analog to digital converter (ADC) at a sub-sampling speed suitable for an intermediate frequency (IF) signal. In some embodiments, a temperature compensation circuit is included. The receiver has an effective noise level less than 7 dB. In some embodiments a 1-bit ADC is used. In some of these embodiments, one or more switches in the ADC are inverted to cancel charge injection.

Claims

1. An apparatus comprising:

a low noise amplifier (LNA) for a radio frequency signal that includes a carrier wave at a carrier wave frequency;

an analog to digital converter (ADC) for a sampling frequency that is much less than the carrier wave frequency; and

a Q-enhanced CMOS bandpass filter that substantively blocks frequencies above half the sampling frequency, wherein the Q-enhanced CMOS bandpass filter is electrically connected between the low noise amplifier and the ADC.

2. An apparatus as recited in claim 1, wherein the apparatus produces a noise level less than about seven deciBels (dB).

3. An apparatus as recited in claim 1, wherein the Q-enhanced CMOS bandpass filter further comprises:

an inductor spiral on an integrated circuit;

a capacitor in parallel with the inductor spiral; and

a negative resistance circuit disposed in parallel with the spiral inductor and capacitor.

4. An apparatus as recited in claim 3, wherein the negative resistance circuit further comprises a cross-coupled pair of transistors.

5. An apparatus as recited in claim 4, further comprising a limiting amplifier configured to compensate for temperature dependence of the pair of transistors.

6. An apparatus as recited in claim 1, wherein the ADC is a one bit ADC.

7. An apparatus as recited in claim 6, wherein the ADC comprises a sampling switch and a second switch that is configured to cancel charge injection by the sampling switch.

8. An apparatus as recited in claim 1, wherein the ADC is configured to sample up to about 250 megaHertz (MHz).

9. An apparatus as recited in claim 1, wherein the LNA is configured to provide a gain of more than about 30 deciBels (dB) and a noise figure less than about 3 dB.

10. An apparatus as recited in claim 1, wherein the LNA is configured to operate on about eight (8) milliWatts (mW) of power.

11. An apparatus as recited in claim 1, wherein the Q-enhanced bandpass filter is configured to provide a full width at −

3 dB of 6*1.023 mega Hert (MHz).

12. An apparatus as recited in claim 11, wherein the ADC is configured to sample at 16*1.023 MHz.

13. A method comprising:

filtering a first radio frequency signal with a Q-enhanced CMOS bandpass filter that substantively blocks frequencies above half a sampling frequency; and

sampling a second radio frequency signal based on a filtered signal output by the Q-enhanced CMOS bandpass filter at or near the sampling frequency.

14. A method as recited in claim 13, further comprising amplifying a received radio frequency signal with a low noise amplifier (LNA) to produce the first radio frequency signal.

15. A method as recited in claim 13, further comprising amplifying the filtered signal output by the Q-enhanced CMOS bandpass filter to produce the second radio frequency signal.

16. A method as recited in claim 13, wherein a sampled signal based on the second radio frequency signal has a noise figure of less than about 3 deciBels (dB).

17. An apparatus comprising:

means for filtering a first radio frequency signal with a Q-enhanced CMOS bandpass filter that substantively blocks frequencies above half a sampling frequency; and

means for sampling a second radio frequency signal based on a filtered signal output by the Q-enhanced CMOS bandpass filter at or near the sampling frequency.

18. An apparatus as recited in claim 17, further comprising means for amplifying a received radio frequency signal with a low noise amplifier (LNA) to produce the first radio frequency signal.

19. An apparatus as recited in claim 17, further comprising means for amplifying the filtered signal output by the Q-enhanced CMOS bandpass filter to produce the second radio frequency signal.

20. An apparatus as recited in claim 17, wherein a sampled signal based on the second radio frequency signal has a noise figure of less than about 3 deciBels (dB).

21. A Q-enhanced CMOS bandpass filter comprising:

an inductor spiral on an integrated circuit;

a capacitor in parallel with the inductor spiral; and

a negative resistance circuit disposed in parallel with the spiral inductor and capacitor.