NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME

• US 20100302860A1
• Filed: 05/26/2010
• Published: 12/02/2010
• Est. Priority Date: 05/29/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Oh, Seung Min
• Granted Patent: US 8,184,483 B2
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A nonvolatile memory device includes a memory cell array, including a first memory cell group configured to store data and a second memory cell group configured to store operation information, including first and second program start voltages, a page buffer unit, including page buffers each configured to store program data for memory cells or store data read from the memory cells, and a control unit configured to, when a program operation is first performed after power is supplied, count a number of program pulses until a verification operation using a first verification voltage is a pass, compare the counted number and a first number of program pulses, select either the first or second program start voltages according to a result of the comparison, and control the program operation to be performed using the selected program start voltage until the power is off.

Claims

1. A nonvolatile memory device, comprising:

a memory cell array configured to comprise a first memory cell group and a second memory cell group, the first memory cell group being coupled to bit lines and word lines and configured to store data, and the second memory cell group being configured to store operation information comprising first and second program start voltages;

a page buffer unit configured to comprise page buffers, each being coupled to one or more of the bit lines and configured to temporarily store data to be programmed into memory cells or to store data read from the memory cells; and

a control unit configured to, when a program operation is first performed after power is supplied, count a number of program pulses until a verification operation using a first verification voltage is a pass, compare the counted number of program pulses and a first number of program pulses included in the operation information, select any one of the first and second program start voltages according to a result of the comparison, and control the program operation to be performed using the selected program start voltage until the power is off.

2. The nonvolatile memory device of claim 1, wherein the control unit comprises:

a counter configured to count the number of program pulses until the verification operation using the first verification voltage is a pass;

a comparator configured to compare the counted number of program pulses and the first number of program pulses, and to output a first flag signal according to a result of the comparison; and

a MUX configured to select one of the first and second program start voltages in response to the first flag signal, and to output the selected program start voltage and a second flag signal in response to the selected program start voltage.

3. The nonvolatile memory device of claim 2, wherein the counter and the comparator stop operating in response to the second flag signal.

4. The nonvolatile memory device of claim 1, wherein the first program start voltage is set by default and applied to a program operation when the nonvolatile memory device is first started.

5. The nonvolatile memory device of claim 4, wherein the control unit changes the selected program start voltage from the first program start voltage to the second program start voltage when the counted number of program pulses is less than the first number of program pulses.

6. The nonvolatile memory device of claim 5, wherein the first program start voltage has a higher voltage level than the second program start voltage.

7. A method of operating a nonvolatile memory device, the method comprising:

performing a program operation by supplying a program voltage starting with a first program start voltage, and storing operation information, including a first number of program pulses when a verification operation using a first verification voltage is a pass, the first program start voltage, and a second program start voltage;

inputting power to the nonvolatile memory device, and loading the operation information;

determining whether a program command received after the power is supplied is received for the first time, and if, as a result of the determination, the received program command is determined to be received for the first time, performing the program operation by supplying a program voltage starting with the first program start voltage, and counting a number of program pulses until the verification operation using the first verification voltage is a pass; and

comparing the counted number of program pulses and the first number of program pulses, and selecting one of the first and second program start voltages as a program start voltage according to a result of the comparison.

8. The method of claim 7, wherein, if, as a result of the determination, the received program command is determined not to be received for the first time, the program operation is performed by supplying the program voltage starting with the selected program start voltage, and the number of program pulses is not counted.

9. The method of claim 7, wherein the first program start voltage has a higher voltage level than the second program start voltage.

10. The method of claim 9, wherein, if, as a result of the comparison, the counted number of program pulses is less than the first number of program pulses, the second program start voltage is selected as the program start voltage.

11. A semiconductor memory device, comprising memory cells for a program and page buffers for temporarily storing data to be programmed in the memory cells or reading data stored in the memory cells and temporarily storing the read data, the semiconductor memory device comprising:

a CAM cell unit configured to store operation information, including first and second program start voltages, and first program pulse information which is a number of program pulses counted until a first verification operation using a first verification voltage is a pass during a program operation first performed after a power source is inputted; and

a control unit configured to select one of the first and second program start voltages based on the stored first program pulse information and control the program operation so that the program operation is performed, when the memory cells are programmed.

12. A method of programming a semiconductor memory device, the method comprising:

during a program operation which is first performed in response to a program command after a power source is inputted, counting a number of program pulses supplied until a first verification operation using a first verification voltage is a pass, and storing the counted number of program pulses as first program pulse information;

setting a program start voltage based on the stored first program pulse information; and

during a program operation which is performed in response to a program command after the first program operation, supplying a program voltage in accordance with an ISPP method based on the set program start voltage.