FABRICATING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE

• US 20100304525A1
• Filed: 08/12/2010
• Published: 12/02/2010
• Est. Priority Date: 07/01/2008
• Status: Active Grant

• Current Assignee: Chunghwa Picture Tubes Limited (Tatung Co., Ltd.)
• Original Assignee: Chunghwa Picture Tubes Limited (Tatung Co., Ltd.)
• Inventors: Chien, Yao-Hong, Liu, Xuan-Yu, Wang, Chih-Chieh, Chen, Li-Shan
• Granted Patent: US 7,968,367 B2
• Time in Patent Office: Days
• US Class Current: 438/73
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A fabricating method of a TFT array substrate includes following steps: providing a substrate having a pixel region and a bonding pad region surrounding the pixel region; forming a patterned polysilicon layer within the pixel region on the substrate; forming a first patterned insulating layer to cover the patterned polysilicon layer; forming a first patterned transparent conductive layer on the first patterned insulating layer; forming a first metal layer on the first patterned transparent conductive layer; forming a second patterned insulating layer to cover the first metal layer; forming a second patterned transparent conductive layer on the second patterned insulating layer; forming a second metal layer on the second patterned transparent conductive layer; forming a third patterned insulating layer to cover the second metal layer; and forming a third patterned transparent conductive layer on the third patterned insulating layer.

Claims

1. A fabricating method of a thin film transistor array substrate, comprising:

providing a substrate, wherein the substrate has a pixel region and a bonding pad region located surrounding the pixel region;

forming a patterned polysilicon layer within the pixel region on the substrate, wherein the patterned polysilicon layer comprises a source and a drain;

forming a first patterned insulating layer to cover the patterned polysilicon layer;

forming a first patterned transparent conductive layer on the first patterned insulating layer;

forming a first metal layer on the first patterned transparent conductive layer, wherein the first metal layer is partially disposed on the first patterned transparent conductive layer and comprises a gate, a scan line electrically connected to the gate and a common line disposed within the pixel region, and a part of the first patterned transparent conductive layer is disposed under the common line;

forming a second patterned insulating layer to cover the first metal layer, wherein the first patterned insulating layer and the second patterned insulating layer have a first contact hole to expose the drain;

forming a second patterned transparent conductive layer on the second patterned insulating layer, wherein a part of the second patterned transparent conductive layer is electrically connected to the drain via the first contact hole;

forming a second metal layer on the second patterned transparent conductive layer, wherein the second metal layer is partially disposed on the second patterned transparent conductive layer and the second metal layer comprises a data line electrically connected to the source, and a part of the second patterned transparent conductive layer is disposed under the data line;

forming a third patterned insulating layer to cover the second metal layer, wherein the third patterned insulating layer has a second contact hole to expose the second patterned transparent conductive layer electrically connected to the drain; and

forming a third patterned transparent conductive layer on the third patterned insulating layer, wherein the third patterned transparent conductive layer comprises a pixel electrode located within the pixel region, and the pixel electrode is electrically connected to the second patterned transparent conductive layer via the second contact hole.

2. The fabricating method of a thin film transistor array substrate according to claim 1, further comprising forming a scan bonding pad within the bonding pad region, wherein the scan bonding pad is electrically connected to the scan line, and the method of forming the scan bonding pad comprises:

forming the first patterned transparent conductive layer within the bonding pad region;

forming the first metal layer on the first patterned transparent conductive layer, wherein the first metal layer has a contact hole; and

forming the third patterned transparent conductive layer on the first metal layer, wherein the third patterned transparent conductive layer is electrically connected to the first patterned transparent conductive layer via the contact hole.

3. The fabricating method of a thin film transistor array substrate according to claim 1, further comprising forming a data bonding pad within the bonding pad region, wherein the data bonding pad is electrically connected to the data line, and the method of forming the data bonding pad comprises:

forming the second patterned transparent conductive layer within the bonding pad region;

forming the second metal layer on the second patterned transparent conductive layer, wherein the second metal layer has a contact hole; and

forming the third patterned transparent conductive layer on the second metal layer, wherein the third patterned transparent conductive layer is electrically connected to the second patterned transparent conductive layer via the contact hole.

4. The fabricating method of a thin film transistor array substrate according to claim 1, further comprising forming the second metal layer on the second patterned transparent conductive layer over the common line, wherein the pixel structure is electrically connected to the second metal layer via the second contact hole.

5. The fabricating method of a thin film transistor array substrate according to claim 1, wherein the method of forming the common line and first patterned transparent conductive layer comprises:

forming a first transparent conductive material layer on the substrate;

forming a first metal material layer on the first transparent conductive material layer; and

taking a half-tone photomask as a mask to conduct a lithography-etching process on the first metal material layer and the first transparent conductive material layer so as to form the common line and the first patterned transparent conductive layer.

6. A fabricating method of a thin film transistor array substrate, comprising:

providing a substrate, wherein the substrate has a pixel region and a bonding pad region located surrounding the pixel region;

forming a first patterned transparent conductive layer on the substrate;

forming a first metal layer on a part of the first patterned transparent conductive layer, wherein the first metal layer comprises a gate, a scan line electrically connected to the gate and a common line within the pixel region, and a part of the first patterned transparent conductive layer is disposed under the common line;

forming a first insulating layer to cover the first metal layer;

forming a channel layer on the first insulating layer over the gate;

forming a second patterned transparent conductive layer on the substrate;

forming a second metal layer on a part of the second patterned transparent conductive layer, wherein the second metal layer comprises a source and a drain respectively disposed at two sides of the channel layer and a data line electrically connected to the source, wherein a part of the second patterned transparent conductive layer is disposed under the drain;

forming a second insulating layer to cover the second metal layer and expose the second patterned transparent conductive layer under the drain; and

forming a third patterned transparent conductive layer on the substrate, wherein the third patterned transparent conductive layer comprises a pixel electrode electrically connected to the second patterned transparent conductive layer under the drain.

7. The fabricating method of a thin film transistor array substrate according to claim 6, wherein the method of forming the common line and the first patterned transparent conductive layer together serving as the lower electrode of a storage capacitor comprises:

forming a first transparent conductive material layer on the substrate;

forming a first metal material layer on the first transparent conductive material layer; and

taking a half-tone photomask as a mask to conduct a lithography-etching process on the first metal material layer and the first transparent conductive material layer so as to form the common line and the first patterned transparent conductive layer.

8. The fabricating method of a thin film transistor array substrate according to claim 6, further comprising forming a scan bonding pad within the bonding pad region, wherein the scan bonding pad is electrically connected to the scan line, and the method of forming the scan bonding pad comprises:

forming the first patterned transparent conductive layer within the bonding pad region;

forming the first metal layer on the first patterned transparent conductive layer, wherein the first metal layer has a contact hole; and

forming the third patterned transparent conductive layer on the first metal layer, wherein the third patterned transparent conductive layer is electrically connected to the first patterned transparent conductive layer via the contact hole.

9. The fabricating method of a thin film transistor array substrate according to claim 6, further comprising forming a data bonding pad within the bonding pad region, wherein the data bonding pad is electrically connected to the data line, and the method of forming the data bonding pad comprises:

forming the second patterned transparent conductive layer within the bonding pad region;

forming the second metal layer on the second patterned transparent conductive layer, wherein the second metal layer has a contact hole; and

forming the third patterned transparent conductive layer on the second metal layer, wherein the third patterned transparent conductive layer is electrically connected to the second patterned transparent conductive layer via the contact hole.