Method of manufacturing layered chip package

• US 20100304531A1
• Filed: 07/30/2010
• Published: 12/02/2010
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Headway Technologies Incorporated (TDK Corporation), TDK Corporation
• Original Assignee: Headway Technologies Incorporated (TDK Corporation), TDK Corporation
• Inventors: Ito, Hiroyuki, Sueki, Satoru, Harada, Tatsuya, Sasaki, Yoshitaka, Okuzawa, Nobuyuki
• Granted Patent: US 7,863,095 B2
• Time in Patent Office: Days
• US Class Current: 438/109
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 Specific sequence of method steps
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces.

Claims

1. A method of manufacturing a layered chip package, the layered chip package comprising a plurality of layer portions stacked, wherein:

each of the plurality of layer portions includes a semiconductor chip having a first surface with a device formed thereon and a second surface opposite to the first surface; and

the plurality of layer portions include at least a pair of layer portions that are disposed such that the first surfaces of the respective semiconductor chips face toward each other,

the method comprising the steps of;

fabricating a layered substructure by stacking a plurality of substructures in correspondence with the order of stacking of the plurality of layer portions of the layered chip package, wherein the plurality of substructures respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions; and

fabricating a plurality of layered chip packages by using the layered substructure,

wherein the step of fabricating the layered substructure includes the steps of;

fabricating a first pre-polishing substructure by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the first pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned;

fabricating a second pre-polishing substructure by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the second pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned;

bonding the first and second pre-polishing substructures to each other such that the respective first surfaces of the first and second pre-polishing substructures face toward each other; and

polishing the respective second surfaces of the first and second pre-polishing substructures in a bonded state so as to obtain a stack of a first substructure and a second substructure, the first substructure being formed by thinning the first pre-polishing substructure by the polishing, the second substructure being formed by thinning the second pre-polishing substructure by the polishing.

2. The method of manufacturing the layered chip package according to claim 1, wherein the step of fabricating the layered substructure further includes the step of bonding a plurality of stacks together, each of the plurality of stacks being fabricated through a series of steps from the step of fabricating the first pre-polishing substructure to the step of polishing.

3. A method of manufacturing a layered chip package, the layered chip package comprising:

a main body having a top surface, a bottom surface and four side surfaces; and

wiring disposed on at least one of the side surfaces of the main body, wherein;

the main body includes a plurality of layer portions stacked;

each of the plurality of layer portions includes;

a semiconductor chip having a first surface with a device formed thereon, a second surface opposite to the first surface, and four side surfaces;

an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and

a plurality of electrodes connected to the semiconductor chip;

the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;

each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed;

the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions; and

the plurality of layer portions include at least a pair of layer portions that are disposed such that the first surfaces of the respective semiconductor chips face toward each other,

the method comprising the steps of;

fabricating a layered substructure by stacking a plurality of substructures in correspondence with the order of stacking of the plurality of layer portions of the layered chip package, wherein the plurality of substructures respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions; and

fabricating a plurality of layered chip packages by using the layered substructure,

wherein the step of fabricating the layered substructure includes the steps of;

fabricating a first pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the first pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned;

fabricating a second pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the second pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned;

fabricating a first pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the first pre-substructure wafer, wherein the first pre-polishing substructure is fabricated through;

forming in the first pre-substructure wafer at least one groove that extends to be adjacent to at least one of the pre-semiconductor-chip portions, the at least one groove opening at the first surface of the first pre-substructure wafer and having a bottom that does not reach the second surface of the first pre-substructure wafer;

forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later; and

forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer;

fabricating a second pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the second pre-substructure wafer, wherein the second pre-polishing substructure is fabricated through;

forming in the second pre-substructure wafer at least one groove that extends to be adjacent to at least one of the pre-semiconductor-chip portions, the at least one groove opening at the first surface of the second pre-substructure wafer and having a bottom that does not reach the second surface of the second pre-substructure wafer;

forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later; and

forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer;

bonding the first and second pre-polishing substructures to each other such that the respective first surfaces of the first and second pre-polishing substructures face toward each other; and

polishing the respective second surfaces of the first and second pre-polishing substructures in a bonded state so as to obtain a stack of a first substructure and a second substructure, the first substructure being formed by thinning the first pre-polishing substructure by the polishing, the second substructure being formed by thinning the second pre-polishing substructure by the polishing.

4. The method of manufacturing the layered chip package according to claim 3, wherein:

the pair of layer portions comprises a first layer portion including a first semiconductor chip and a second layer portion including a second semiconductor chip;

the first semiconductor chip includes a plurality of first terminals aligned in a predetermined order;

the second semiconductor chip includes a plurality of second terminals aligned in a predetermined order in correspondence with the first terminals;

the first layer portion includes, as the plurality of electrodes, a plurality of first electrodes connected to the plurality of first terminals;

the second layer portion includes, as the plurality of electrodes, a plurality of second electrodes connected to the plurality of second terminals; and

as seen in one direction under a condition in which the first and second layer portions are disposed such that the respective first surfaces of the first and second semiconductor chips face toward each other, the order in which the second terminals are aligned is the reverse of the order in which the first terminals are aligned, the end faces of the first electrodes located at the at least one of the side surfaces of the main body are aligned in an order that is the same as the order in which the corresponding first terminals are aligned, and the end faces of the second electrodes located at the at least one of the side surfaces of the main body are aligned in an order that is the reverse of the order in which the corresponding second terminals are aligned.

5. The method of manufacturing the layered chip package according to claim 3, wherein, in the step of polishing, the second surface of the first pre-polishing substructure is polished until the at least one groove of the first pre-polishing substructure becomes exposed, and the second surface of the second pre-polishing substructure is polished until the at least one groove of the second pre-polishing substructure becomes exposed.

6. The method of manufacturing the layered chip package according to claim 3, wherein the step of fabricating the layered substructure further includes the step of bonding a plurality of stacks together, each of the plurality of stacks being fabricated through a series of steps from the step of fabricating the first pre-substructure wafer to the step of polishing.

7. The method of manufacturing the layered chip package according to claim 6, wherein:

in each of the step of fabricating the first pre-polishing substructure and the step of fabricating the second pre-polishing substructure, an alignment mark is formed on the insulating layer simultaneously with the formation of the plurality of electrodes; and

in the step of bonding the plurality of stacks together, alignment of the plurality of stacks is performed using the alignment mark.

8. The method of manufacturing the layered chip package according to claim 7, wherein the insulating layer is transparent.

9. The method of manufacturing the layered chip package according to claim 3, wherein:

the step of fabricating a plurality of layered chip packages includes the steps of;

forming a main body aggregate by cutting the layered substructure, the main body aggregate including a plurality of pre-main-body portions each of which will later become the main body, the plurality of pre-main-body portions being aligned in one direction that is orthogonal to a stacking direction of the plurality of layer portions;

forming the wiring for each of the pre-main-body portions of the main body aggregate; and

cutting the main body aggregate after the formation of the wiring so as to separate the plurality of pre-main-body portions from each other so that each of them becomes the main body and the plurality of layered chip packages are thereby formed,

wherein, in the step of forming the main body aggregate, the insulating layer is cut to form a cut surface along a direction in which the at least one groove extends, whereby part of the at least one end face of the insulating portion is formed by the cut surface of the insulating layer and the end faces of the plurality of electrodes are exposed.

10. The method of manufacturing the layered chip package according to claim 9, wherein, in the step of forming the wiring, a plurality of the main body aggregates are arranged in the stacking direction of the plurality of layer portions and then the wiring is formed for each of the pre-main-body portions of the plurality of the main body aggregates.

11. The method of manufacturing the layered chip package according to claim 10, wherein:

in each of the step of fabricating the first pre-polishing substructure and the step of fabricating the second pre-polishing substructure, an alignment mark is formed on the insulating layer simultaneously with the formation of the plurality of electrodes; and

in the step of forming the wiring, alignment of the plurality of the main body aggregates to be arranged in the stacking direction of the plurality of layer portions is performed using the alignment mark.

12. The method of manufacturing the layered chip package according to claim 11, wherein the insulating layer is transparent.