SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

• US 20100304540A1
• Filed: 08/12/2010
• Published: 12/02/2010
• Est. Priority Date: 11/17/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Hun, Kang, Sung-Taeg, Han, Jeong-Uk, Jeon, Hee-Seog
• Application Number:
  US12/855,371
• Publication Number:
  US 20100304540A1
• Time in Patent Office: Days
• US Class Current: 438/261
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Claims

1. A method of forming a semiconductor device, comprising:

forming a first conductive layer pattern on a substrate;

forming a stacked pattern including an inter-gate insulation layer pattern and a second conductive layer pattern on the first conductive layer pattern;

forming a mask insulation layer pattern on the first conductive layer pattern spaced apart from the stacked pattern;

removing the first conductive layer pattern outside the stacked pattern and the mask insulation layer pattern to form a floating gate below the stacked pattern, and to form a selection gate below the mask insulation layer pattern;

forming a floating junction on the substrate between the floating gate and the selection gate; and

forming a spacer on one sidewall of the stacked pattern adjacent to the selection gate after the forming of the floating junction,

wherein the spacer completely covers the floating junction between the floating gate and the selection gate, and extends toward a sidewall of the selection gate.

2. The method of claim 1, wherein the forming of the mask insulation layer comprises:

forming a spacer on at least one sidewall of the stacked pattern;

forming the mask insulation layer pattern on the first conductive layer pattern exposed outside the spacer; and

removing the spacer.

3. The method of claim 2, wherein the forming of the spacer on at least one sidewall of the stacked pattern comprises:

forming an insulation layer for the spacer;

forming a photoresist pattern exposing a sidewall of the stacked pattern with the spacer thereon; and

etching the insulation layer for a spacer exposed by the photoresist pattern.

4. The method of claim 2, wherein the forming of the spacer on at least one sidewall of the stacked pattern comprises:

forming an insulation layer for the spacer; and

etching the insulation layer for the spacer,

wherein the spacer is formed on both sidewalls of the stacked pattern, the selection gate is formed on the substrate in both sides of the floating gate, the floating junction is formed between the floating gate and the selection gates on both sides of the floating gate.

5. The method of claim 2, wherein the forming of the spacer on at least one sidewall of the stacked pattern comprises:

forming an insulation layer for the spacer;

etching the insulation layer for a spacer to form spacers on both sidewalls of the stacked pattern;

forming a mask pattern covering one of the spacers and exposing another spacer;

removing the spacer exposed by the mask pattern; and

removing the mask pattern.

6. The method of claim 3, further comprising forming an oxide layer on the both sidewalls of the stacked pattern before the forming of the insulation for the spacer.

7. The method of claim 3, wherein the insulation layer for the spacer is formed of a silicon nitride layer.

8. The method of claim 7, further comprising forming an oxide layer on the both sidewall of the stacked pattern before the forming the insulation layer for the spacer.

9. The method of claim 2, wherein the mask insulation layer pattern is formed using a thermal oxidation process on the first conductive layer pattern exposed outside the spacer.

10. The method of claim 1, further comprising:

forming a drain in the substrate outside the stacked pattern not adjacent to the floating junction, and a source in the substrate outside the selection gate not adjacent to the floating junction through an ion implantation process.

11. A method of forming a semiconductor device, comprising:

forming a conductive layer pattern on a substrate;

forming a stacked pattern including an inter-layer insulation layer and a control gate on the conductive layer pattern;

forming a spacer on at least one sidewall of the stacked pattern;

forming a mask insulation layer pattern on the conductive layer pattern exposed outside of the spacer;

removing the spacer;

etching the conductive layer pattern outside the stacked pattern to form a floating gate below the stacked pattern and to form a selection gate below the mask insulation layer pattern;

performing a first ion implantation process to form a floating junction on a substrate between the floating gate and the selection gate; and

performing a second ion implantation process to form a source and a drain on the substrate outside the floating gate and the selection gate not adjacent to the floating junction.

12. The method of claim 11, further comprising forming an oxide layer on both sidewalls of the stacked pattern before the forming of the spacer.

13. The method of claim 11, wherein the inter-layer insulation layer includes silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO).

14. The method of claim 11, wherein the forming of the mask insulation layer pattern comprises performing a thermal oxidation process on the conductive layer pattern exposed outside the spacer.

15. The method of claim 11, wherein the spacer is formed on both sidewalls of the stacked pattern;

the selection gate is formed on the substrate in both sides of the floating gate; and

the floating junction region is formed between the floating gate and the selection gates in the both sides of the floating gate.

16. The method of claim 11, further comprising forming a second spacer on one

sidewall of the stacked pattern adjacent to the selection gate after the performing of the first ion implantation process to form the floating junction,

wherein the second spacer completely covers the floating junction, and extends toward a sidewall of the selection gate sidewall.