METHOD AND APPARATUS FOR USING ATRIAL DISCRIMINATION ALGORITHMS TO DETERMINE OPTIMAL PACING THERAPY AND THERAPY TIMING

• US 20100305639A1
• Filed: 07/15/2010
• Published: 12/02/2010
• Est. Priority Date: 11/14/2000
• Status: Abandoned Application

• Current Assignee: David S. Wood, Milton M. Morris, Victor T. Chen
• Original Assignee: David S. Wood, Milton M. Morris, Victor T. Chen
• Inventors: Morris, Milton M., Chen, Victor T., Wood, David S.
• Application Number:
  US12/836,784
• Publication Number:
  US 20100305639A1
• Time in Patent Office: Days
• US Class Current: 607/15
• CPC Class Codes: A61N 1/3622 comprising two or more electrodes co-operating with different heart regions

Abstract

A system and method which employs atrial discrimination algorithms to distinguish between different atrial arrhythmias occurring in a patient for selecting an optimal pacing therapy corresponding to the type of arrhythmia identified. In response to the detection of an atrial rate above the atrial tracking rate, discrimination criteria are applied to a detected atrial activity signal to distinguish between different types of supraventricular tachycardia, such as fast atrial flutter and other atrial flutter at a relatively slower rate, which may be occurring in the patient. The pacer is controlled to provide pacing therapy to a heart in a manner corresponding to the type of supraventricular tachycardia identified. The output of an atrial discrimination algorithm may be tracked and the trend thereof used to improve therapy timing. Various embodiments are disclosed herein.

Claims

1. A cardiac pacing device for pacing a heart, comprising:

a pacer configured to pace the heart;

an atrial activity detector configured to detect atrial activity; and

a processor connected to a memory, wherein the memory is configured to store instructions and the processor is configured to operate on the instructions, wherein the instructions stored in the memory include an atrial discrimination algorithm for distinguishing between fast atrial flutter at a first high rate and another atrial flutter at a second lower rate, wherein the processor is connected to the atrial activity detector and to the pacer, and wherein the processor is configured to operate on the instructions in the memory to determine if the detected atrial activity is fast atrial flutter at the first high rate or the other atrial flutter at the second lower rate, and to control the pacer to provide a first pacing therapy for the fast atrial flutter and to provide a second pacing therapy for the other atrial flutter.

2. The device of claim 1, wherein the pacer is configured to deliver atrial antitachycardia pacing, and the processor is configured to operate on the instructions in the memory to control the pacer to deliver the atrial antitachycardia pacing when the atrial activity is determined to be the other atrial flutter at the second lower rate.

3. The device of claim 1, wherein the pacer is configured to deliver ventricular pacing, and the processor is configured to operate on the instructions in the memory to control the pacer to deliver the ventricular pacing when the atrial activity is determined to be the fast atrial flutter at the second lower rate.

4. The device of claim 3, wherein the pacer is configured to deliver ventricular rate regulation.

5. The device of claim 3, wherein the pacer is configured to deliver rate smoothing pacing.

6. The device of claim 1, wherein:

the pacer is configured to deliver atrial antitachycardia pacing and ventricular pacing; and

the processor is configured to operate on the instructions in the memory to control the pacer to deliver the atrial antitachycardia pacing when the atrial activity is determined to be the other atrial flutter at the second lower rate, and to deliver the ventricular pacing when the atrial activity is determined to be the fast atrial flutter at the second lower rate.

7. The device of claim 1, wherein the atrial discrimination algorithm stored in the memory includes rate-based discrimination criteria.

8. The device of claim 1, wherein the atrial discrimination algorithm stored in the memory includes morphology-based discrimination criteria.

9. The device of claim 1, wherein the atrial discrimination algorithm stored in the memory includes a multi-dimensional threshold function for comparison against a plurality of statistics calculated from the atrial activity signal.

10. The device of claim 1, wherein the instructions stored in the memory include instructions, operable on by the processor, for providing ventricular pacing pulses at a pacing rate based on a detected atrial rate up to a maximum pacing rate, and instructions, operable on by the processor, for applying the atrial discrimination algorithm only if the detected atrial rate exceeds the maximum atrial tracking rate.

11. A cardiac pacing device for pacing a heart, comprising:

a pacer configured to provide atrial pacing and ventricular pacing to the heart;

an atrial activity sensor configured to sense atrial activity;

a signal detector connected to the atrial activity sensor and configured to detect atrial depolarizations from the sensed atrial activity; and

a processor connected to a memory, wherein the memory is configured to store instructions and the processor is configured to operate on the instructions, wherein the instructions stored in the memory include an atrial discrimination algorithm for distinguishing between fast atrial flutter at a first high rate and another atrial flutter at a second lower rate, wherein the processor is connected to the signal detector and to the pacer, and wherein the processor is configured to operate on the instructions in the memory to determine if the atrial activity is fast atrial flutter at the first high rate or the other atrial flutter at the second lower rate, and to control the pacer to provide ventricular pacing for the fast atrial flutter and to provide atrial pacing for the other atrial flutter.

12. The device of claim 11, wherein the pacer is configured to deliver ventricular pacing with ventricular rate regulation.

13. The device of claim 11, wherein the pacer is configured to deliver ventricular pacing with rate smoothing.

14. The device of claim 11, wherein the atrial pacing includes atrial antitachycardia pacing.

15. The device of claim 11, wherein the atrial discrimination algorithm stored in the memory includes rate-based discrimination criteria.

16. The device of claim 11, wherein the atrial discrimination algorithm stored in the memory includes morphology-based discrimination criteria.

17. The device of claim 11, wherein the atrial discrimination algorithm stored in the memory includes a multi-dimensional threshold function for comparison against a plurality of statistics calculated from the atrial activity signal.

18. The device of claim 11, wherein the instructions stored in the memory include instructions, operable on by the processor, for providing ventricular pacing pulses at a pacing rate based on a detected atrial rate up to a maximum pacing rate, and instructions, operable on by the processor, for applying the atrial discrimination algorithm only if the detected atrial rate exceeds the maximum atrial tracking rate.

19. A cardiac pacing device for pacing a heart, comprising:

a pacer configured to provide atrial pacing and ventricular pacing to the heart;

an atrial activity detector configured to detect atrial activity; and

a processor connected to a memory, wherein the memory is configured to store instructions and the processor is configured to operate on the instructions, wherein the instructions stored in the memory include an atrial discrimination algorithm for distinguishing between fast atrial flutter at a first high rate and another atrial flutter at a second lower rate, wherein the atrial discrimination algorithm stored in the memory includes rate-based discrimination criteria, morphology-based discrimination criteria, or a multi-dimensional threshold function for comparison against a plurality of statistics calculated from the atrial activity signal, wherein the instructions stored in the memory include instructions, operable on by the processor, for providing ventricular pacing pulses at a pacing rate based on a detected atrial rate up to a maximum pacing rate, and instructions, operable on by the processor, for applying the atrial discrimination algorithm only if the detected atrial rate exceeds the maximum atrial tracking rate, wherein the processor is connected to the atrial activity detector and to the pacer, and wherein the processor is configured to operate on the instructions in the memory when a rate of detected atrial activity exceeds the maximum atrial tracking rate to determine if the atrial activity is fast atrial flutter at the first high rate or the other atrial flutter at the second lower rate, and to control the pacer to provide ventricular pacing for the fast atrial flutter and to provide atrial anti-tachycardia pacing for the other atrial flutter.

20. The device of claim 19, wherein the pacer is configured to deliver ventricular pacing with ventricular rate regulation.

21. The device of claim 19, wherein the pacer is configured to deliver ventricular pacing with rate smoothing.