DMA TRANSFER DEVICE

• US 20100306421A1
• Filed: 08/09/2010
• Published: 12/02/2010
• Est. Priority Date: 03/03/2008
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: MAEDA, Takashi, Yamamoto, Daisuke
• Application Number:
  US12/853,092
• Publication Number:
  US 20100306421A1
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A source address setting detector acquires a DMA source address from a transfer start address setting for a DMA source area of a plurality of register settings for a DMAC which are made by a master. A read-ahead processor reads ahead data in a resource which is specified by the DMA source address before the DMAC starts DMA transfer, and further, increments the DMA source address to repeat read-ahead operation. The DMAC starts DMA transfer if the master completes the register settings, reads data in the DMA source area which has already been read ahead in the read-ahead processor, and transfers the data to a DMA destination area in the resource.

Claims

1. A DMA transfer device comprising:

a direct memory access controller (DMAC);

a master configured to control the DMAC;

at least one resource configured to be accessed in direct memory access (DMA) transfer;

a source address setting detector configured to acquire a DMA source address from a transfer start address setting for a DMA source area of register settings for the DMAC which are made by the master in order to start DMA transfer; and

a read-ahead processor configured to issue a read request to the DMA source address in the resource detected by the source address setting detector.

7. The DMA transfer device of claim 1, further comprising:

a read-ahead data storing buffer configured to store data read ahead according to the read request output from the read-ahead processor.

8. The DMA transfer device claim 1, further comprising:

a cache configured to store data read ahead according to the read request output from the read-ahead processor.

9. The DMA transfer device of claim 1, further comprising:

a shared cache configured to store data read ahead according to the read request output from the read-ahead processor, the shared cache being shared by the DMAC and one or more bus masters.

10. The DMA transfer device of claim 9, wherein

the shared cache includes a plurality of caches,

at least one of the plurality of caches is exclusively used by the DMAC, and

the data read ahead according to the read request output from the read-ahead processor is stored into the cache exclusively used by the DMAC.

11. The DMA transfer device of claim 8, wherein

the read-ahead data is stored into a DMA source address area in the cache or the shared cache, and is written to a DMA destination by storing a copy of the data into a DMA destination address area in the cache or the shared cache.

12. The DMA transfer device of claim 11, wherein

the DMA source address area in the cache or the shared cache into which the copy of the data has been stored is invalidated.

13. The DMA transfer device claim 8, wherein

the read-ahead data is stored into a DMA source address area in the cache or the shared cache, and is written to a DMA destination by changing a tag of the DMA source address area in the cache or the shared cache to a tag of a DMA destination address area.

14. The DMA transfer device of claim 8, wherein

the read-ahead data is stored into a DMA destination address area in the cache or the shared cache.

15. The DMA transfer device of claim 11, further comprising:

an attribute specifier configured to write a cache attribute to a tag area of the cache when the read-ahead data is written to a destination address area in the cache or the shared cache.

16. The DMA transfer device of claim 1, wherein

after issuing the read request, the read-ahead processor increments the DMA source address and issues another read request.

17. The DMA transfer device of claim 16, further comprising:

a read-ahead end address holder,

wherein

when the DMA source address reaches an address held by the read-ahead end address holder, the incrementation is stopped and read-ahead operation is ended.

18. The DMA transfer device of claim 16, further comprising:

a total-number-of-transfer-operations measurer configured to measure the number of times that the read-ahead processor issues a read request; and

a total-number-of-transfer-operations holder configured to hold an upper limit of the total number of transfer operations which can be measured by the total-number-of-transfer-operations measurer,

wherein

when a value measured by the total-number-of-transfer-operations measurer reaches the upper limit held by the total-number-of-transfer-operations holder, read-ahead operation is ended.

19. The DMA transfer device of claim 16, further comprising:

a number-of-successive-read-ahead-operations measurer configured to measure the number of times that the read-ahead processor issues a read request before the DMAC issues a read request; and

a number-of-successive-read-ahead-operations holder configured to hold an upper limit of the number of successive read ahead operations which can be measured by the number-of-successive-read-ahead-operations measurer,

wherein

when a value measured by the number-of-successive-read-ahead-operations measurer reaches the upper limit held by the number-of-successive-read-ahead-operations holder, read-ahead operation is stopped.

20. The DMA transfer device of claim 1, wherein

read-ahead operation is performed by single transfer.

21. The DMA transfer device of claim 1, wherein

read-ahead operation is performed by burst transfer.

22. The DMA transfer device of claim 1, wherein

when block transfer is performed, read-ahead operation is performed.

23. The DMA transfer device of claim 1, wherein

activation and inactivation of the read-ahead processor can be controlled.

24. The DMA transfer device of claim 1, further comprising:

a DMA transfer size detector configured to acquire a DMA transfer size from a DMA transfer size setting indicating how many words are to be DMA-transferred of the register settings for the DMAC which are made by the master in order to start DMA transfer.

2. A DMA transfer device comprising:

a direct memory access controller (DMAC) including a plurality of transfer channels;

a master configured to control the direct memory access controller (DMAC);

at least one resource configured to be accessed in DMA transfer;

a source address setting detector configured to acquire a DMA source address for each of the transfer channels, from a transfer start address setting for a DMA source area of register settings which are made by the master for the each of the transfer channels of the DMAC in order to start the corresponding DMA transfer; and

a read-ahead processor,

wherein

the read-ahead processor includes one or more read-ahead channels configured to hold the DMA source addresses detected by the source address setting detector,

the read-ahead processor issues a read request to the DMA source address in the resource held by each of the read-ahead channels.

3. The DMA transfer device of claim 2, further comprising:

a DMA transfer controller configured to request the master not to start any more DMA transfer when all of the read-ahead channels are being used.

4. The DMA transfer device of claim 2, wherein

when all of the read-ahead channels are being used, a DMA source address is not stored into any of the read-ahead channels in DMA transfer in one of the transfer channels which is newly started by the master.

5. The DMA transfer device of claim 2, wherein

a DMA source address is not stored into any of the read-ahead channels in DMA transfer other than those of one or more specific ones of the transfer channels.

6. The DMA transfer device of claim 2, further comprising:

an arbiter configured to arbitrate between read requests output from the plurality of read-ahead channels.