DETECTING LOST AND OUT OF ORDER POSTED WRITE PACKETS IN A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS NETWORK

• US 20100306442A1
• Filed: 06/02/2009
• Published: 12/02/2010
• Est. Priority Date: 06/02/2009
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gregg, Thomas A.
• Application Number:
  US12/476,861
• Publication Number:
  US 20100306442A1
• Time in Patent Office: Days
• US Class Current: 710/313
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

An article of manufacture, an apparatus, and a method for processing packets in a peripheral component interconnect express (PCIe) network. An article of manufacture includes a computer program product that includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a PCIe posted write packet at a receiving device, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device. An expected tag identifier is determined for the requesting device. The received tag identifier is compared to the expected tag identifier. An error flag is set if the received tag identifier does not match the expected tag identifier.

Claims

1. A computer program product for processing packets in a peripheral component interconnect express (PCIe) network, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

receiving a PCIe posted write packet at a receiving device, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device;

determining an expected tag identifier for the requesting device;

comparing the received tag identifier to the expected tag identifier; and

setting an error flag in response to the received tag identifier not matching the expected tag identifier.

2. The computer program product of claim 1, wherein the method further comprises incrementing the expected tag identifier for the requesting device in response to the comparing being completed.

3. The computer program product of claim 1, wherein the received tag identifier and the expected tag identifier are synchronized periodically between the requesting device and the receiving device.

4. The computer program product of claim 1, wherein the receiving device is a root complex device in a PCIe network, and the determining an expected tag identifier includes accessing a device table that is indexed by requesting device identifiers.

5. The computer program product of claim 1, wherein the receiving device is an endpoint in a PCIe network, and the determining an expected tag identifier includes reading a register corresponding to the requesting device.

6. A system for processing packets in a PCIe network, the system comprising:

a receiver in communication with a PCIe switch for receiving a PCIe posted write packet, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device;

a storage mechanism for storing an expected tag identifier for the requesting device;

a comparator for comparing the received tag identifier to the expected tag identifier and setting an error flag in response to the received tag identifier not matching the expected tag identifier.

7. The system of claim 6, further comprising an incrementor for incrementing the expected tag identifier for the requesting device in response to the comparing being completed.

8. The system of claim 6, wherein the received tag identifier and the expected tag identifier are synchronized periodically between the requesting device and the receiving device.

9. The system of claim 6, wherein the receiving device is a PCIe root complex device, and the storage mechanism includes a device table that is indexed by requesting device identifiers.

10. The system of claim 6, wherein the receiving device is a PCIe endpoint, and the storage mechanism includes a register corresponding to the requesting device.

11. A method for processing packets in a PCIe network, the method comprising:

receiving a PCIe posted write packet at a receiving device, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device;

determining an expected tag identifier for the requesting device;

comparing the received tag identifier to the expected tag identifier; and

setting an error flag in response to the received tag identifier not matching the expected tag identifier.

12. The method of claim 11, wherein the method further comprises incrementing the expected tag identifier for the requesting device in response to the comparing being completed.

13. The method of claim 11, wherein the received tag identifier and the expected tag identifier are synchronized periodically between the requesting device and the receiving device.

14. The method of claim 11, wherein the receiving device is a root complex device in a PCIe network, and the determining an expected tag identifier includes accessing a device table that is indexed by requesting device identifiers.

15. The method of claim 11, wherein the receiving device is an endpoint in a PCIe network, and the determining an expected tag identifier includes reading a register corresponding to the requesting device.

16. A computer program product for processing packets in a peripheral component interconnect express (PCIe) network, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

accessing at a requesting device a PCIe posted write packet identifying a receiving device;

determining a current tag identifier corresponding to the receiving device;

inserting the current tag identifier into a tag field in the posted write packet; and

transmitting posted write packet to the receiving device.

17. The computer program product of claim 16, wherein the method further comprises incrementing the current tag identifier corresponding to the receiving device in response to the inserting being completed.

18. The computer program product of claim 16, wherein the current tag identifier at the requesting device is synchronized periodically with an expected tag identifier at the receiving device.

19. The computer program product of claim 16, wherein the requesting device is a root complex device in the PCIe network, and the determining a current tag identifier includes accessing one or more of an address lookup table and a down-bound tag table.

20. The computer program product of claim 16, wherein the requesting device is an endpoint in a PCIe network, and the determining a current tag identifier includes reading a register corresponding to the receiving device.

21. A system for processing packets in a PCIe network, the system comprising:

a posted write packet mechanism at a requesting device for accessing a PCIe posted write packet that identifies a receiving device and for inserting a current tag identifier corresponding to the receiving device into a tag field in the posted write packet;

a storage mechanism at the requesting device for storing the current tag identifier corresponding to the receiving device;

a transmitter at the requesting device in communication with a PCIe switch for transmitting the PCIe posted write packet to the receiving device via the PCIe switch.

22. The system of claim 21, further comprising an incrementor at the requesting device for incrementing the current tag identifier corresponding to the receiving device in response to the inserting being completed.

23. The system of claim 21, wherein the current tag identifier at the requesting device is synchronized periodically with an expected tag identifier at the receiving device.

24. The system of claim 21, wherein the requesting device is a root complex device in a PCIe network and the storage mechanism comprises one or more of an address lookup table and a down-bound tag table.

25. The system of claim 21, wherein the requesting device is an endpoint in a PCIe network, and the storage mechanism comprises a register.