CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE

• US 20100306448A1
• Filed: 05/27/2009
• Published: 12/02/2010
• Est. Priority Date: 05/27/2009
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Chen, Richard, Hsueh, Rex, Hou, Ping
• Granted Patent: US 8,271,737 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/214 Solid state disk

Abstract

A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted.

Claims

1. A solid state memory device comprising:

a solid state non-volatile memory array;

a cache coupled to the non-volatile memory array; and

a processor arranged to control the writing of data from the cache to the non-volatile memory array and operative to enable actions including;

starting a threshold time period when the cache contains dirty data;

re-starting the threshold time period on receipt of one of a plurality of host commands;

writing the dirty data to the non-volatile memory array on expiration of the threshold time period; and

terminating the writing of dirty data to the non-volatile memory array and re-starting the threshold time period when the cache contains dirty data either on receipt of one of the plurality of host commands or after a last set of dirty data from the cache is written to the non-volatile memory.

2. The memory device of claim 1, wherein the processor is operative to further enable actions including:

determining that the cache contains dirty data; and

determining the threshold time period based on a timer.

3. The memory device of claim 1, wherein the processor is operative to further enable actions including:

setting the threshold time period so that the writing of the dirty data to the non-volatile memory does not exceed a maximum number of write accesses for a predicted life span of the non-volatile memory.

4. The memory device of claim 1, wherein the processor is further operative to enable actions including:

setting the threshold time period based on the number of dirty entries in the cache or the frequency of host commands.

5. The memory device of claim 1, wherein writing the dirty data to the non-volatile memory array takes place according to an amount of time that the dirty data has remained in the cache.

6. The memory device of claim 1, wherein writing the dirty data to the non-volatile memory array includes application of wear-leveling techniques.

7. The memory device of claim 1, wherein the non-volatile memory array is NAND flash memory.

8. A method for managing caching comprising:

determining that a memory cache contains dirty data;

starting a threshold time period when the memory cache contains dirty data;

re-starting the threshold time period on receiving a host command of a plurality of host commands;

writing the dirty data from the memory cache to a solid state non-volatile memory array on expiration of the threshold time period; and

terminating the writing of dirty data from the memory cache to the solid state non-volatile memory array and re-starting the threshold time period when the cache contains dirty data either on receipt of a host command of the plurality of host commands or after a last set of dirty data from the cache is written to the solid state non-volatile memory.

9. The method of claim 8, wherein the threshold time period is determined based on a timer.

10. The method of claim 8, wherein the threshold time period is set so that the writing of the dirty data to the non-volatile memory does not exceed a maximum number of write accesses for a predicted life span of the non-volatile memory.

11. The method of claim 8, further comprising:

setting the threshold time period based on the number of dirty entries in the cache or the frequency of host commands.

12. The method of claim 8, wherein writing the dirty data to the non-volatile memory array takes place according to an amount of time that the dirty data has remained in the cache.

13. The method of claim 8, wherein writing the dirty data to the non-volatile memory array includes application of wear-leveling techniques.

14. The method of claim 8, wherein the non-volatile memory array is NAND flash memory.

15. A solid state drive comprising:

a host interface;

a solid state non-volatile memory array;

a cache coupled to the host interface and the non-volatile memory array; and

a processor for controlling the writing of data from the cache to the non-volatile memory array and operative to enable actions including;

starting a threshold time period when the cache contains dirty data;

re-starting the threshold time period on receipt of one of a plurality of host commands;

writing the dirty data to the non-volatile memory array on expiration of the threshold time period; and

terminating the writing of dirty data to the non-volatile memory array and re-starting the threshold time period either on receipt of one of the plurality of host commands or after a last set of dirty data from the cache is written to the non-volatile memory.

16. The drive of claim 15, wherein the processor is operative to enable further actions including:

determining the threshold time period based on a timer.

17. The drive of claim 15, wherein the processor is operative to enable further actions including:

setting the threshold time period so that the writing of the dirty data to the non-volatile memory does not exceed a maximum number of write accesses for a predicted life span of the non-volatile memory.

18. The drive of claim 15, wherein the processor is further operative to enable actions for:

setting the threshold time period based on the number of dirty entries in the cache or the frequency of host commands.

19. The drive of claim 15, wherein writing the dirty data to the non-volatile memory array takes place according to an amount of time that the dirty data has remained in the cache.

20. The drive of claim 15, wherein writing the dirty data to the non-volatile memory array includes application of wear-leveling techniques.