I-CACHE LINE USE HISTORY BASED DONE BIT BASED ON SUCCESSFUL PREFETCHABLE COUNTER

• US 20100306472A1
• Filed: 05/28/2009
• Published: 12/02/2010
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A.
• Granted Patent: US 8,140,760 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/127 using additional replacement algorithms

Abstract

A method of providing history based done logic for a I-cache includes receiving an I-cache line in an L2 cache; determining if the I-cache line is unprefetchable; aging the I-cache line without a delay if the I-cache line is prefetchable; and aging the I-cache line with a delay is the I-cache line is unprefetchable.

Claims

1. A method of providing history based done logic for a I-cache, the method comprising:

receiving an I-cache line in an L2 cache;

determining if the I-cache line is unprefetchable;

aging the I-cache line without a delay if the I-cache line is prefetchable; and

aging the I-cache line with a delay is the I-cache line is unprefetchable.

2. The method of claim 1, wherein the I-cache line includes a demand stall flag and an aging flag.

3. The method of claim 2, wherein the I-cache line includes a history count and a reference count.

4. The method of claim 3, wherein the determining further comprises updating the reference count in an L1 I-cache and the L2 I-cache each time the I-cache line is accessed.

5. The method of claim 2, further comprising aging the I-cache line at a rate indicated by the aging flag if a demand stall flag indicates that I-cache line is unprefetchable.

6. An integrated circuit device comprising:

a processor core;

a level one (L1) cache;

a level two (L2) cache; and

an aging count in the L1 cache for indicating a number of least recently used demotions to be skipped between actual demotions to an I-cache line in the L1 cache.

7. The integrated circuit device of claim 6, wherein the I-cache line includes a demand stall flag and an aging flag.

8. The integrated circuit device of claim 7, further comprising a counter that counts each time the I-cache line is referenced in the L1 cache.

9. The integrated circuit device of claim 8, further comprising a comparator for comparing a history count to a reference count to determine when the reference count is equal to the history count for a I-cache line.

10. The integrated circuit device of claim 9, wherein the counter updates a reference counter in the L2 cache each time the I-cache line is referenced in the L1 cache.

11. The integrated circuit device of claim 7, wherein the I-cache line is aged at a rate indicated by the aging flag if a demand stall flag indicates that I-cache line is unprefetchable.

12. A processor device comprising:

a level one (L1) cache;

a level two (L2) cache; and

circuitry configured to receive an I-cache line in the L2 cache, determine if the I-cache line is unprefetchable, age the I-cache line without a delay if the I-cache line is prefetchable, and age the I-cache line with a delay if the I-cache line is unprefetchable.

13. The processor device of claim 12, wherein the I-cache line includes a demand stall flag and an aging flag.

14. The processor device of claim 13, wherein the I-cache line includes a history count and a reference count.

15. The processor device of claim 14, wherein the determining further comprises updating the reference count in the L1 I-cache and L2 I-cache each time the I-cache line is accessed.

16. The processor device of claim 12, further comprising aging the I-cache line at a rate indicated by the aging flag if a demand stall flag indicates that I-cache line is unprefetchable.