CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO D-CACHE REPLACEMENT SCHEME

• US 20100306473A1
• Filed: 05/28/2009
• Published: 12/02/2010
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A.
• Granted Patent: US 8,291,169 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value

Abstract

A method of providing history based done logic includes receiving a cache line in a L2 cache; determining if the cache line has a history of access at least three times on a previous call into the L2 cache; providing the cache line directly to a processor if the history of access was less then the at least three times; and loading the cache line into an L1 cache if the history of access was the at least three times.

Claims

1. A method of providing history based done logic, the method comprising:

receiving a cache line in a L2 cache;

determining if the cache line has a history of access at least three times on a previous call into the L2 cache;

providing the cache line directly to a processor if the history of access was less then the at least three times; and

loading the cache line into an L1 cache if the history of access was the at least three times.

2. The method of claim 1, wherein the cache line includes a history count and a reference count.

3. The method of claim 2, further comprising incrementing the reference count each time the cache line is accessed.

4. The method of claim 3, wherein the determining further comprises:

comparing a history count to a reference count; and

marking the cache line in the L1 cache as least recently used when the history count equals the reference count.

5. The method of claim 2, further comprising updating the reference count in the L1 cache and L2 cache each time the cache line is accessed.

6. The method of claim 1, further comprising loading the cache line into a data line buffer for access by the processor if the history of access is equal to two.

7. An integrated circuit device, comprising:

a processor core;

a level one cache;

a level two cache; and

a history count in the level one cache for indicating a number of load references to the cache line a last time the cache line was called in to the level one cache.

8. The integrated circuit device of claim 7, further comprising a comparator for comparing the history count to a reference count to determine when the reference count is equal to the history count.

9. The integrated circuit device of claim 8, further comprising a counter that counts each time the cache line is referenced in the L1 cache.

10. The integrated circuit device of claim 9, wherein the counter updates a reference counter in the L2 cache each time the cache line is referenced in the L1 cache.

11. The integrated circuit device of claim 10, further comprising a loader that loads the cache line into a data line buffer for access by the processor if the history of access is equal to two.

12. A processor device, comprising:

a level one cache;

a level two cache; and

circuitry configured to;

receive a cache line in a L2 cache;

determine if the cache line has a history of access at least three times on a previous call into the L2 cache;

provide the cache line directly to a processor if the history of access was less then the at least three times; and

load the cache line into an L1 cache if the history of access was the at least three times.

13. The processor device of claim 12, wherein the cache line includes a history count and a reference count.

14. The processor device of claim 13, further comprising a counter that updates the reference count in the L1 cache each time the cache line is referenced in the L1 cache.

15. The processor device of claim 14, wherein the counter updates the reference count in the L2 cache each time the cache line is accessed.

16. The processor device of claim 12, further comprising:

a comparator that compares the history count to the reference count; and

a counter that marks the cache line in the L1 cache as least recently used when the history count equals the reference count.

17. The processor device of claim 16, further comprising a confidence counter that counts each time the reference count is greater than the history count.

18. The processor device of claim 12, further comprising a loader that loads the cache line into a data line buffer for access by the processor if the history of access is equal to two.