CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO I-CACHE REPLACEMENT SCHEME

• US 20100306474A1
• Filed: 05/28/2009
• Published: 12/02/2010
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A.
• Granted Patent: US 8,332,587 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

A method of providing history based done logic for instructions includes receiving an instruction in a cache line in a L2 cache; and loading the cache line into an L1 cache with a history count that indicates the number of read references of the previous access.

Claims

1. A method of providing history based done logic for instructions, the method comprising:

receiving an instruction in a cache line in a L2 cache; and

loading the cache line into an L1 cache with a history count that indicates the number of read references of the previous access.

2. The method of claim 1, wherein the cache line includes a reference count set originally to zero.

3. The method of claim 2, further comprising incrementing the reference count each time the cache line is branched into.

4. The method of claim 3, further comprising:

comparing the history count to a into an L1 cache with a history count that indicates the number of read references of the reference count; and

marking the cache line in the L1 cache as least recently used when the history count equals the reference count.

5. The method of claim 2, further comprising updating the reference count in the L1 cache and L2 cache each time the cache line is read.

6. The method of claim 1, further comprising updating the reference count in the L1 cache and L2 cache each time the cache line is incremented into.

7. An integrated circuit device, comprising:

a processor core;

a level one cache;

a level two cache; and

a history count in the level one cache for indicating a number of read references to an instruction in a cache line a last time the cache line was called in to the level one cache.

8. The integrated circuit device of claim 7, further comprising a comparator for comparing the history count to a reference count to determine when the reference count is equal to the history count.

9. The integrated circuit device of claim 8, further comprising a counter that counts each time the cache line is referenced in the L1 cache.

10. The integrated circuit device of claim 9, wherein the counter updates a reference counter in the L2 cache each time the cache line is referenced in the L1 cache.

11. A processor device, comprising:

a level one cache;

a level two cache;

circuitry configured to;

receive an instruction in a cache line in a L2 cache and loading the cache line into an L1 cache with a history count that indicates the number of read references of the previous access.

12. The processor device of claim 11, wherein the cache line includes a reference count.

13. The processor device of claim 12, further comprising a counter that updates the reference count in the L1 cache each time the cache line is referenced in the L1 cache.

14. The processor device of claim 13, wherein the counter updates the reference count in the L2 cache each time the cache line is branched into.

15. The processor device of claim 11, wherein the counter updates the reference count in the L2 cache each time the cache line is incremented into.

16. The processor device of claim 11, further comprising:

a comparator that compares the history count to the reference count; and

a counter that marks the cache line in the L1 cache as least recently used when the history count equals the reference count.

17. The processor device of claim 15, further comprising a confidence counter that counts each time the reference count is greater than the history count.