Systems and Methods for Governing the Life Cycle of a Solid State Drive

• US 20100306580A1
• Filed: 05/28/2009
• Published: 12/02/2010
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Warren, Robert W., McKean, Brian D., Dreifus, David L.
• Granted Patent: US 8,151,137 B2
• Time in Patent Office: Days
• US Class Current: 714/8
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

Various embodiments of the present invention provide systems and methods for data storage. As an example, storage devices are disclosed that include a plurality of memory blocks, an unreliable block identification circuit, and a partial failure indication circuit. Each of the plurality of memory blocks includes a plurality of memory cells that decrease in reliability over time as they are accessed. The unreliable block identification circuit is operable to determine that one or more of the plurality of memory blocks is unreliable, and the partial failure indication circuit is operable to disallow write access to the plurality of memory blocks upon determination that an insufficient number of the plurality of memory blocks remain reliable.

Claims

1. A storage device, wherein the storage device comprises:

a plurality of memory portions each including a plurality of memory cells, wherein a reliability of the memory cells decreases over time as the memory portions are accessed;

an unreliable block identification circuit, wherein the unreliable block identification circuit is operable to determine that one or more of the plurality of memory portions is unreliable; and

a partial failure indication circuit, wherein the partial failure indication circuit is operable to disallow write access to the plurality of memory portions upon determination that an insufficient number of the plurality of memory portions remain reliable.

2. The storage device of claim 1, wherein a subset of the plurality of memory cells is addressable at an interface of the storage device, and wherein the storage device further includes a control circuit, and wherein upon determining that one or more of the plurality of memory portions is unreliable, the control circuit is operable to move data stored in the one or more unreliable memory portions to one or more reliable memory portions.

3. The storage device of claim 1, wherein each of the plurality of memory cells is a plurality of flash memory cells.

4. The storage device of claim 1, wherein the plurality of memory portions can be reliably read at the point when the partial failure indication circuit disallowed write access to the plurality of memory portions.

5. The storage device of claim 1, wherein the storage device further comprises:

a time stamp circuit, wherein the time stamp circuit is operable to identify a point in time when the partial failure indication circuit disallowed write access to the plurality of memory portions.

6. The storage device of claim 5, wherein the time stamp circuit includes:

a timer circuit that provides the point in time.

7. The storage device of claim 5, wherein the storage device is communicably coupled to a host, and wherein the point in time is provided by the host to the time stamp circuit.

8. The storage device of claim 5, wherein the point in time is a first point in time, and wherein the storage device further comprises:

an end of life indication circuit, wherein the end of life indication circuit is operable to estimate a second point in time based at least in part on the first point in time, wherein the second point in time indicates when the ability to read one or more of the plurality of memory portions can no longer be guaranteed.

9. The storage device of claim 8, wherein the end of life indication circuit adds a fixed time increment to the first point in time.

10. The storage device of claim 9, wherein the fixed time increment is a predefined estimate of how long data will remain readable in the plurality of memory cells after the determination that an insufficient number of the plurality of memory portions remain reliable.

11. A method for governing the life cycle of a storage device, the method comprising:

providing a plurality of memory cells;

determining that a subset of the plurality of memory cells is unreliable; and

based at least in part upon the determination that the subset of the plurality of memory cells is unreliable, disallowing future write accesses to the plurality of memory cells.

12. The method of claim 11, wherein the subset of the plurality of memory cells is a first subset of the plurality of memory cells, and wherein the method further comprises:

receiving a write request, wherein the write request is directed to a second subset of the plurality of memory cells; and

indicating a write error to a host providing the write request.

13. The method of claim 11, wherein the plurality of memory cells are arranged in a first number of memory portions, wherein the subset of the plurality of memory cells includes a second number of memory portions, wherein the first number is greater than the second number, and wherein each of the memory portions includes a third number of memory cells.

14. The method of claim 11, wherein the subset of the plurality of memory cells is a first subset of the plurality of memory cells, and wherein the method further comprises:

receiving a read request, wherein the read request is directed to a second subset of the plurality of memory cells;

accessing the second subset of the plurality of memory cells; and

providing data gathered from accessing the second subset of the plurality of memory cells to a host providing the read request.

15. The method of claim 11, wherein the memory cells are flash memory cells, and wherein determining that a subset of the plurality of memory cells is unreliable includes performing a process selected from a group consisting of:

identifying an increase in time required for performing a program erase cycle to the subset of the plurality of memory cells, and identifying an error rate increase related to data written to the subset of the plurality of memory cells.

16. The method of claim 11, wherein the plurality of memory cells are implemented in a storage device, and wherein the method further comprises:

determining a point in time when the last portion of the subset of the plurality of memory cells were determined to be unreliable; and

storing the point in time in a register implemented in the storage device.

17. The method of claim 11, wherein the plurality of memory cells are implemented in a storage device, and wherein the method further comprises:

determining a point in time when the last portion of the subset of the plurality of memory cells were determined to be unreliable;

determining an estimated failure time of the storage device, wherein the estimated time is determined by adding a fixed time increment to the point in time; and

storing the estimated failure time in a register implemented in the storage device.

18. The method of claim 17, wherein the fixed time increment is a predefined estimate of how long data will remain readable in the plurality of memory cells after the point in time.

19. The method of claim 11, wherein the plurality of memory cells are implemented in a storage device, wherein the method further comprises:

determining a point in time when the last portion of the subset of the plurality of memory cells were determined to be unreliable;

determining an estimated failure time of the storage device, wherein the estimated time is determined by adding a fixed time increment to the point in time; and

reporting the estimated failure time to a host communicably coupled to the storage device.

20. A solid state drive, the solid state drive comprising:

a first number of memory portions each including a plurality of flash memory cells, wherein a second number of the first number of memory portions are addressable, and wherein a difference between the first number and the second number is an over provisioned number of memory portions;

a control circuit, wherein the controller circuit includes;

an unreliable block identification circuit, wherein the unreliable block identification circuit is operable to determine that one or more of the first number of memory portions is unreliable, and wherein upon determining that one or more of the first number of memory portions is unreliable the over provisioned number of memory portions is reduced; and

a partial failure indication circuit, wherein the partial failure indication circuit is operable to disallow write access to any of the memory portions upon determination that the over provisioned number of memory portions is less than or equal to a threshold level;

a time stamp circuit, wherein the time stamp circuit is operable to identify a first point in time when the partial failure indication circuit disallowed write access to the memory portions; and

an end of life indication circuit, wherein the end of life indication circuit is operable to estimate a second point in time when the ability to read one or more of the plurality of memory portions can no longer be guaranteed by adding a fixed time increment to the point in time, wherein the fixed time increment is a predefined estimate of how long data will remain readable in the memory cells after the first point in time.