ARRAY SUBSTRATE FOR DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20100308324A1
• Filed: 12/04/2009
• Published: 12/09/2010
• Est. Priority Date: 06/03/2009
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Yong-Yub, Ryoo, Chang-Il
• Granted Patent: US 8,158,466 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern. Further, the exposed portion of the auxiliary pattern exposes a channel region and including a metal oxide over the channel region. Also included is a data line over the gate insulating layer, the data line crossing the gate line to define the pixel region and being connected to the source electrode, a passivation layer on the source and drain electrodes and the data line, the passivation layer having a drain contact hole exposing the drain electrode, and a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the drain contact hole.

Claims

1. An array substrate, comprising:

a substrate having a pixel region;

a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line;

a gate insulating layer on the gate line and the gate electrode;

an oxide semiconductor layer on the gate insulating layer;

an auxiliary pattern on the oxide semiconductor layer;

source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, said exposed portion of the auxiliary pattern exposing a channel region and including a metal oxide over the channel region;

a data line over the gate insulating layer, the data line crossing the gate line to define the pixel region and being connected to the source electrode;

a passivation layer on the source and drain electrodes and the data line, the passivation layer having a drain contact hole exposing the drain electrode; and

a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the drain contact hole.

2. The array substrate of claim 1, wherein the metal oxide over the channel region includes titanium oxide.

3. The array substrate of claim 2, wherein other portions other than the exposed portion of the auxiliary pattern include one of titanium and titanium alloy.

4. The array substrate of claim 1, wherein the oxide semiconductor layer includes one of amorphous indium gallium zinc oxide (a-IGZO) and zinc tin oxide (ZTO).

5. The array substrate of claim 1, wherein the oxide semiconductor layer has a thickness of about 500 Å

to about 1000 Å

, and the auxiliary pattern has a thickness of about 50 Å

to about 500 Å

.

6. The array substrate of claim 1, further comprising:

first and second dummy patterns between the data line and the gate insulating layer.

7. The array substrate of claim 6, wherein the first dummy pattern has a same material and a same layer as the oxide semiconductor layer, and the second dummy pattern has a same material and a same layer as other portions other than the exposed portion of the auxiliary pattern.

8. A method of fabricating an array substrate, the method comprising:

forming a gate line and a gate electrode on a substrate having a pixel region, the gate electrode being connected to the gate line;

forming a gate insulating layer on the gate line and the gate electrode;

forming an oxide semiconductor layer and an auxiliary pattern on the gate insulating layer, the auxiliary pattern including a conducting material;

forming source and drain electrodes on the auxiliary pattern and a data line over the gate insulating layer, the source and drain electrodes being disposed over a first portion of the auxiliary pattern and spaced apart from each other to expose a second portion of the auxiliary pattern over a channel region, the data line crossing the gate line to define the pixel region;

oxidizing the second portion of the auxiliary pattern of the conducting material into an insulating material;

forming a passivation layer on the source and drain electrodes and the data line, the passivation layer having a drain contact hole exposing the drain electrode; and

forming a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the drain contact hole.

9. The method of claim 8, wherein the oxidized second portion of the auxiliary pattern includes titanium oxide.

10. The method of claim 8, wherein the first portion of the auxiliary pattern includes one of titanium and titanium alloy.

11. The method of claim 8, wherein the oxide semiconductor layer includes one of amorphous indium gallium zinc oxide (a-IGZO) and zinc tin oxide (ZTO).

12. The method of claim 8, wherein the forming the oxide semiconductor layer and the auxiliary pattern and forming the source and drain electrodes and the data line comprise:

forming an oxide semiconductor material layer, an auxiliary material layer including one of titanium and titanium oxide, and a metal layer on the gate insulating layer through a sputtering method;

forming first and second photoresist patterns on the metal layer, a thickness of the first photoresist pattern being greater than a thickness of the second photoresist pattern;

patterning the metal layer, the auxiliary material layer and the oxide semiconductor material layer using the first and second photoresist patterns as an etching mask to form the auxiliary pattern on the oxide semiconductor layer, and a source-drain pattern on the auxiliary pattern and the data line over the gate insulating layer;

removing the second photoresist pattern through an ashing method, the source-drain pattern being exposed through the first photoresist pattern;

patterning the source-drain pattern using the first photoresist pattern as an etching mask to form the source and drain electrodes on the auxiliary pattern; and

removing the first photoresist pattern.

13. The method of claim 8, wherein the forming the oxide semiconductor layer and the auxiliary pattern and forming the source and drain electrodes and the data line comprise:

forming an oxide semiconductor material layer and an auxiliary material layer including one of titanium and titanium oxide on the gate insulating layer through a sputtering method;

patterning the auxiliary material layer and the oxide semiconductor material layer to form the oxide semiconductor layer on the gate insulating layer and the auxiliary pattern on the oxide semiconductor layer;

forming a metal layer on the auxiliary pattern; and

patterning the metal layer to form the source and drain electrodes on the auxiliary pattern and the data line on the gate insulating layer.

14. The method of claim 8, wherein the oxidizing the second portion of the auxiliary pattern comprises treating the substrate having the second portion of the auxiliary pattern with an oxygen plasma in a vacuum chamber.

15. The method of claim 8, wherein the oxidizing the second portion of the auxiliary pattern comprises treating the substrate having the second portion of the auxiliary pattern with a heat in one of an oven and a furnace of a temperature of about 300°

C. to about 400°

C. for a time period of about several tens of seconds to about several tens of minutes.

16. The method of claim 8, wherein the oxide semiconductor layer has a thickness of about 500 Å

to about 1000 Å

, and the auxiliary pattern has a thickness of about 50 Å

to about 500 Å

.

17. The method of claim 8, further comprising:

forming first and second dummy patterns between the data line and the gate insulating layer.

18. The method of claim 17, wherein the first dummy pattern is simultaneously formed with the oxide semiconductor layer, and the second dummy pattern is simultaneously formed with the first portion of the auxiliary pattern.