3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES

• US 20100308402A1
• Filed: 06/08/2009
• Published: 12/09/2010
• Est. Priority Date: 06/08/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kinzer, Dan, Jo, Seokjin, Calafut, Dan, Kim, Suku, Challa, Ashok, Ho, Ihsiu, Larsen, Mark, Sapp, Steven
• Granted Patent: US 8,072,027 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate containing a source region in an upper portion of the substrate;

a dual trench structure in an upper portion of the substrate, wherein the dual trench structure contains with a plurality of lower trenches extending in both x- and y-directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate the source region;

an oxide layer located on the bottom, sidewall of the lower trenches, and sidewall of the upper trench;

a first portion of a conductive or semi-conductive layer located on the oxide layer in the lower trenches; and

a second portion of a conductive or semi-conductive layer located on the first conductive layer and the mesa.

2. The device of claim 1, wherein the device contains channels extending in the x, y, and z directions to form a three dimensional channel structure.

3. The device of claim 1, wherein the upper portion of the lower trenches opens into the lower portion of the upper trench.

4. The device of claim 1, wherein the oxide layer is also located on an upper portion of the mesa.

5. The device of claim 4, wherein the current flows through the dual trench structure in three dimensions.

6. The device of claim 1, wherein the width of the lower trenches in the x direction is more than the length of the mesa separating adjacent lower trenches.

7. The device of claim 1, wherein the width of the lower trenches ranges from about 0.01 to about 10 μ

m and the length ranges from about 0.01 to about 10 μ

m.

8. The device of claim 1, wherein the first portion of a conductive or semi-conductive layer forms a first layer and the second portion of a different conductive or semi-conductive layer forms a second layer.

9. The device of claim 8, wherein the first portion is deposited to cover the mesa and the second layer is deposited on the first layer.

10. A trench MOSFET device containing a three dimensional channel architecture, comprising:

a silicon substrate with an epitaxial layer in an upper portion thereof, the epitaxial region containing a source region in an upper portion thereof;

a dual trench structure in an upper portion of the substrate, wherein the dual trench structure contains with a plurality of lower trenches extending in an x- and y-direction and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate the source region;

a gate oxide layer located on the bottom, sidewall of the lower trenches, and sidewall of the upper trench;

a polysilicon gate located on the oxide layer in the lower trenches;

a conductive layer located on the polysilicon gate and the mesa and in the upper trench; and

an insulating layer located on the conductive layer in the upper trench between the source region.

11. The device of claim 10, wherein the device contains channels extending in the x, y, and z directions to form a three dimensional channel structure.

12. The device of claim 10, wherein the oxide layer is also located on an upper portion of the mesa.

13. The device of claim 12, wherein the current flows through the dual trench structure in three dimensions.

14. The device of claim 10, wherein the width of the lower trenches in the x direction is more than the length of the mesa separating adjacent lower trenches.

15. The device of claim 10, wherein the width of the lower trenches ranges from about 0.01 to about 10 μ

m and the length ranges from about 0.01 to about 10 μ

m.

16. The device of claim 10, wherein the mesa width between the lower trenches can be adjusted to control the threshold voltage and the inversion layer without changing the doping profile.

17. The device of claim 10, further comprising a shield oxide layer and a conductive shield surrounding the epitaxial layer.

19. The device of claim 10, wherein the oxide layer is also located on an upper portion of the mesa.

20. The device of claim 10, wherein the width of the lower trenches in the x direction is more than the length of the mesa separating adjacent lower trenches.

21. The device of claim 10, wherein the width of the lower trenches ranges from about 0.01 to about 10 μ

m and the length ranges from about 0.01 to about 10 μ

m.

22. The device of claim 10, wherein the mesa width between the lower trenches can be adjusted to control the threshold voltage and the inversion layer without changing the doping profile.

23. The device of claim 10, further comprising a shield oxide layer and a conductive shield surrounding the epitaxial layer.

18. A trench MOSFET device containing a three dimensional channel architecture, comprising:

a silicon substrate with an epitaxial layer in an upper portion thereof, the epitaxial region containing a source region in an upper portion thereof;

a dual trench structure in an upper portion of the substrate, wherein the dual trench structure contains with a plurality of lower trenches extending in an x- and y-direction and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate the source region, thereby forming channels extending in the x, y, and z directions and making a three dimensional channel structure so that current flows through the dual trench structure in three dimensions;

a gate oxide layer located on the bottom, sidewall of the lower trenches, and sidewall of the upper trench;

a polysilicon gate located on the oxide layer in the lower trenches;

a conductive layer located on the polysilicon gate and the mesa and in the upper trench; and

an insulating layer located on the conductive layer in the upper trench between the source region.