CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES

• US 20100308412A1
• Filed: 06/03/2009
• Published: 12/09/2010
• Est. Priority Date: 06/03/2009
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Ando, Takashi, Narayanan, Vijay, Jagannathan, Hemanth
• Granted Patent: US 8,680,629 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.

Claims

1. A material stack formed on a semiconductor substrate of a semiconductor structure, comprising:

a high-k dielectric having a high dielectric constant greater than approximately 3.9;

a germanium (Ge) material layer disposed interfacing with the high-k dielectric; and

a conductive electrode layer disposed above the high-k dielectric or the Ge material layer.

2. The material stack of claim 1, further comprising a conductive layer disposed on top of the conductive electrode layer.

3. The material stack of claim 2, wherein the conductive layer comprises one of a Si-containing conductive layer or a metallic conductive layer.

4. The material stack of claim 1, further comprising a chemical oxide, a thermal oxide or a oxynitride layer disposed beneath the Ge material layer or the high-k dielectric.

5. The material stack of claim 1, wherein the Ge material layer comprises Ge or a Ge compound.

6. The material stack of claim 1, wherein the Ge material layer is disposed beneath the high-k dielectric, and the conductive electrode layer is disposed above the high-k dielectric.

7. The material stack of claim 1, wherein the Ge material layer is disposed on top of the high-k dielectric, and the conductive electrode layer is disposed above the Ge material layer.

8. The material stack of claim 1, wherein a thickness of the Ge material layer is less than or equal to approximately 2 nanometers (nm).

9. The material stack of claim 7, wherein an amount of shift in threshold voltage corresponds to the thickness and a location of the Ge material layer.

10. A semiconductor structure, comprising:

a patterned material stack disposed on a surface of a semiconductor substrate, the patterned material stack comprising;

a high-k dielectric having a high dielectric constant greater than approximately 3.9;

a germanium (Ge) material layer interfacing with the high-k dielectric; and

a conductive electrode layer located above the high-k dielectric or the Ge material layer.

11. A semiconductor structure comprising:

a first semiconductor device having a first patterned material stack disposed on a semiconductor substrate; and

a second semiconductor device having a second patterned material stack disposed on the semiconductor substrate, the first patterned material stack and the second patterned material stack, each comprising;

a high-k dielectric having a high dielectric constant greater than approximately 3.9,

at least one of a metal oxide or nitride layer, or a Ge material layer interfacing with the high-k dielectric, and

a conductive electrode layer located above the high-k dielectric or the Ge material layer, or the metal oxide or nitride layer.

12. The semiconductor structure of claim 11, wherein the first semiconductor device is a n-type field effect transistor and the second semiconductor device is a p-type field effect transistor.

13. The semiconductor structure of claim 11, wherein the metal oxide or nitride layer comprises at least one of an alkaline or a rare earth metal-containing material.

14. The semiconductor structure of claim 11, wherein the first patterned material stack comprises the metal oxide or nitride layer disposed above the high-k dielectric and the second patterned material stack comprises the Ge material layer disposed below the high-k dielectric.

15. The semiconductor structure of claim 11, wherein the first patterned material stack comprises the metal oxide or nitride layer disposed above the high-k dielectric and the second patterned material stack comprises the Ge material layer disposed below the high-k dielectric and the metal oxide or nitride layer disposed above the high-k dielectric.

16. The semiconductor structure of claim 11, wherein the first patterned material stack comprises the metal oxide or nitride layer disposed below the high-k dielectric and the second material stack comprises the Ge material layer disposed above the high-k dielectric.

17. The semiconductor structure of claim 11, wherein the first patterned material stack comprises the metal oxide or nitride layer disposed below the high-k dielectric and the Ge material layer disposed above the high-k dielectric, and the second patterned material stack comprises the Ge material layer disposed above the high-k dielectric.

18. The semiconductor structure of claim 11, wherein the first patterned material stack comprises the metal oxide or nitride layer disposed below the high-k dielectric, and the second patterned material stack comprises the Ge material layer disposed below the high-k dielectric.

20. The semiconductor structure of claim 11, wherein the first patterned material stack comprises the metal oxide or nitride layer disposed above the high-k dielectric, and the second patterned material stack comprises the Ge material layer disposed above the high-k dielectric.

22. A semiconductor structure, comprising:

a patterned material stack disposed on a surface of a semiconductor substrate, the patterned material stack comprising;

a high-k dielectric having a high dielectric constant greater than approximately 3.9; and

a germanium (Ge)-containing metal electrode interfacing with the high-k dielectric.

23. The semiconductor structure of claim 22, wherein the Ge-containing metal electrode comprises MGe where M denotes any conductive metal electrode material.

24. The semiconductor structure of claim 22, wherein the Ge-containing metal electrode is disposed on top of the high-k dielectric.

25. A method of forming a semiconductor structure having a first semiconductor device including a first patterned material stack and a second semiconductor device including a second patterned material stack, the method comprising:

providing a semiconductor substrate;

forming a high-k dielectric having a high dielectric constant greater than approximately 3.9;

forming a metal oxide or nitride layer in the first patterned material stack interfacing with the high-k dielectric;

forming a Ge material layer in the second patterned material stack interfacing with the high-k dielectric; and

forming a conductive electrode layer above the high-k dielectric, the Ge material layer, or the metal oxide or nitride layer.

26. The method of claim 25, further comprising:

forming the Ge material layer in the first patterned material stack interfacing with the high-k dielectric.

27. The method of claim 25, further comprising:

forming the metal oxide or nitride layer in the second patterned material stack interfacing with the high-k-dielectric.