CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES
First Claim
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1. A material stack formed on a semiconductor substrate of a semiconductor structure, comprising:
- a high-k dielectric having a high dielectric constant greater than approximately 3.9;
a germanium (Ge) material layer disposed interfacing with the high-k dielectric; and
a conductive electrode layer disposed above the high-k dielectric or the Ge material layer.
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Abstract
A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.
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Citations
27 Claims
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1. A material stack formed on a semiconductor substrate of a semiconductor structure, comprising:
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a high-k dielectric having a high dielectric constant greater than approximately 3.9; a germanium (Ge) material layer disposed interfacing with the high-k dielectric; and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor structure, comprising:
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a patterned material stack disposed on a surface of a semiconductor substrate, the patterned material stack comprising; a high-k dielectric having a high dielectric constant greater than approximately 3.9; a germanium (Ge) material layer interfacing with the high-k dielectric; and a conductive electrode layer located above the high-k dielectric or the Ge material layer.
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11. A semiconductor structure comprising:
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a first semiconductor device having a first patterned material stack disposed on a semiconductor substrate; and a second semiconductor device having a second patterned material stack disposed on the semiconductor substrate, the first patterned material stack and the second patterned material stack, each comprising; a high-k dielectric having a high dielectric constant greater than approximately 3.9, at least one of a metal oxide or nitride layer, or a Ge material layer interfacing with the high-k dielectric, and a conductive electrode layer located above the high-k dielectric or the Ge material layer, or the metal oxide or nitride layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 20)
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22. A semiconductor structure, comprising:
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a patterned material stack disposed on a surface of a semiconductor substrate, the patterned material stack comprising; a high-k dielectric having a high dielectric constant greater than approximately 3.9; and a germanium (Ge)-containing metal electrode interfacing with the high-k dielectric. - View Dependent Claims (23, 24)
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25. A method of forming a semiconductor structure having a first semiconductor device including a first patterned material stack and a second semiconductor device including a second patterned material stack, the method comprising:
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providing a semiconductor substrate; forming a high-k dielectric having a high dielectric constant greater than approximately 3.9; forming a metal oxide or nitride layer in the first patterned material stack interfacing with the high-k dielectric; forming a Ge material layer in the second patterned material stack interfacing with the high-k dielectric; and forming a conductive electrode layer above the high-k dielectric, the Ge material layer, or the metal oxide or nitride layer. - View Dependent Claims (26, 27)
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Specification