SEMICONDUCTOR DEVICE

• US 20100308421A1
• Filed: 04/26/2010
• Published: 12/09/2010
• Est. Priority Date: 06/05/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: TAMURA, Masaki, MUTO, Akira, FUJIKI, Atsushi, KOIKE, Nobuya, MACHIDA, Yuichi
• Granted Patent: US 9,024,423 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49537 Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H02M 3/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

The size of a semiconductor device is reduced. A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin portion. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with the area positioned directly above a gate pad electrode of the lower semiconductor chip. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other.

Claims

1. A semiconductor device comprising:

a terminal for drain;

a first semiconductor chip placed over the terminal for drain;

a terminal for source-drain and a first terminal for gate placed over the first semiconductor chip;

a second semiconductor chip placed over the terminal for source-drain;

a terminal for source and a second terminal for gate placed over the second semiconductor chip; and

an encapsulation resin portion sealing the first semiconductor chip and the second semiconductor chip and part of the terminal for drain, part of the terminal for source-drain, part of the first terminal for gate, part of the terminal for source, and part of the second terminal for gate,

wherein the first semiconductor chip includes;

a first back surface opposed to the terminal for drain and having a first back surface drain electrode formed therein; and

a first main surface positioned on the opposite side to the first back surface and having a first electrode for source and a first electrode for gate formed therein,

wherein the second semiconductor chip includes;

a second back surface opposed to the terminal for source-drain and having a second back surface drain electrode formed therein; and

a second main surface positioned on the opposite side to the second back surface and having a second electrode for source and a second electrode for gate formed therein,

wherein the first back surface drain electrode of the first semiconductor chip is electrically couple with the terminal for drain through a conductive bonding material,

wherein the first electrode for gate of the first semiconductor chip is electrically coupled with the first terminal for gate through a conductive bonding material,

wherein the first electrode for source of the first semiconductor chip is electrically coupled with the terminal for source-drain through a conductive bonding material,

wherein the second back surface drain electrode of the second semiconductor chip is electrically coupled with the terminal for source-drain through a conductive bonding material,

wherein the second electrode for gate of the second semiconductor chip is electrically coupled with the second terminal for gate through a conductive bonding material,

wherein the second electrode for source of the second semiconductor chip is electrically coupled with the terminal for source through a conductive bonding material, and

wherein the first semiconductor chip and the second semiconductor chip are so arrange that the second semiconductor chip does not overlap with the area positioned directly above the first electrode for gate of the first semiconductor chip.

2. The semiconductor device according to claim 1,

wherein the first semiconductor chip and the second semiconductor chip are arranged with their respective centers displaced from each other so that the second semiconductor chip does not overlap with the area positioned directly above the first electrode for gate of the first semiconductor chip.

3. The semiconductor device according to claim 2,

wherein the first semiconductor chip and the second semiconductor chip are identical in size, and

wherein the shape and arrangement of the first electrode for source and the first electrode for gate in the first semiconductor chip are the same as the shape and arrangement of the second electrode for source and the second electrode for gate in the second semiconductor chip.

4. The semiconductor device according to claim 3,

wherein the arrangement of the second semiconductor chip corresponds to the arrangement obtained by rotating the first semiconductor chip by 180°

.

5. The semiconductor device according to claim 4,

wherein the second semiconductor chip and the first semiconductor chip partly planarly overlap with each other.

6. The semiconductor device according to claim 5,

wherein the terminal for source does not planarly overlap with the first electrode for gate of the first semiconductor chip.

7. The semiconductor device according to claim 6,

wherein the surface of the terminal for drain on the opposite side to the side where the terminal for drain is opposed to the first semiconductor chip is exposed from the first main surface of the encapsulation resin portion.

8. The semiconductor device according to claim 7,

wherein the terminal for drain is thicker than the terminal for source-drain, the first terminal for gate, the terminal for source, and the second terminal for gate.

9. The semiconductor device according to claim 8,

wherein part of each of the terminal for source-drain, the first terminal for gate, the terminal for source, and the second terminal for gate is protruded from the lateral surface of the encapsulation resin portion and is bent outside the encapsulation resin portion.

10. The semiconductor device according to claim 9,

wherein the terminal for drain is not bent.

11. The semiconductor device according to claim 10,

wherein the first main surface side of the encapsulation resin portion is the mounting surface of the semiconductor device.

12. The semiconductor device according to claim 11,

wherein a high-side MOSFET of a DC-DC converter is formed in the first semiconductor chip, and

wherein a low-side MOSFET of the DC-DC converter is formed in the second semiconductor chip.

13. The semiconductor device according to claim 12,

wherein the first back surface drain electrode, first electrode for source, and first electrode for gate of the first semiconductor chip are respectively electrically coupled to the drain, source, and gate of the high-side MOSFET, and

wherein the second back surface drain electrode, second electrode for source, and second electrode for gate of the second semiconductor chip are respectively electrically coupled to the drain, source, and gate of the low-side MOSFET.

14. The semiconductor device according to claim 13,

wherein the width of the terminal for source-drain and the width of the terminal for source outside the encapsulation resin portion are larger than the width of the first terminal for gate and the width of the second terminal for gate outside the encapsulation resin portion.

15. The semiconductor device according to claim 5,

wherein the surfaces of the terminal for source and the second terminal for gate on the opposite side to the side where the terminal for source and the second terminal for gate are opposed to the second semiconductor chip are exposed from the second main surface of the encapsulation resin portion.

16. The semiconductor device according to claim 15,

wherein part of each of the terminal for drain, the terminal for source-drain, and the first terminal for gate is protruded from the lateral surface of the encapsulation resin portion and is bent outside the encapsulation resin portion.

17. The semiconductor device according to claim 16,

wherein the second main surface of the encapsulation resin portion is the mounting surface of the semiconductor device.

18. The semiconductor device according to claim 17,

wherein the terminal for source and the second terminal for gate are thicker than the terminal for drain, the terminal for source-drain, and the first terminal for gate.

19. The semiconductor device according to claim 18,

wherein the terminal for source or the second terminal for gate is not bent.