INTEGRATED PACKAGE
First Claim
1. An integrated semiconductor device including:
- a device substrate with a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface; and
an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring;
wherein the device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element;
the integrated semiconductor device further comprising;
electrical interconnects across the interconnection major surface; and
interconnection bumps outside the sealing ring, the interconnection bumps electrically connecting the device electrical connectors to the interconnects.
2 Assignments
0 Petitions
Accused Products
Abstract
A device substrate has a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface. An interconnection substrate has an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring. The device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. Electrical interconnects extend across the interconnection major surface. Interconnection bumps are provided outside the sealing ring to electrically connect the device to the interconnect substrate.
26 Citations
11 Claims
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1. An integrated semiconductor device including:
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a device substrate with a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface; and an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring; wherein the device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element; the integrated semiconductor device further comprising; electrical interconnects across the interconnection major surface; and interconnection bumps outside the sealing ring, the interconnection bumps electrically connecting the device electrical connectors to the interconnects. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An interconnection substrate for mounting a device substrate having a device major surface, a semiconductor element on the device major surface, and device electrical connectors on the device major surface, wherein the interconnection substrate comprises:
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an interconnection major surface; electrical interconnects extending across the interconnection major surface; at least one sealing recess recessed from the interconnection major surface; a sealing ring surrounding the sealing recess; bonding pads around and outside the sealing ring for connecting through interconnection bumps to the device electrical connectors on the device major surface so that the device substrate may be mounted on the interconnection substrate with the interconnection major surface facing the device major surface, with the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. - View Dependent Claims (8)
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9. A method of mounting a device substrate having a device major surface, a semiconductor element on the device major surface, and device electrical connectors on the device major surface, the method comprising:
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providing an interconnection substrate having an interconnection major surface and electrical interconnects across the interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring; forming interconnection bumps on the electrical interconnects or the electrical connection pads; aligning the device substrate with the interconnection substrate with the interconnection major surface facing the device major surface, with the sealing ring around the semiconductor element; and
with the interconnection bumps aligned between the device electrical connectors and the interconnects; andbonding the device substrate to the interconnection substrate with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element and with the interconnection bumps connect the device electrical connectors and the electrical interconnects. - View Dependent Claims (10, 11)
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Specification